Resistance variable memory elements based on polarized silver-selenide network growth

Abstract

The invention relates to a resistance variable memory element including polarizable metal-chalcogen regions within a doped chalcogenide glass. A method for physically aligning the polarizable metal-chalcogen regions to form a conducting channel is provided. The invention also relates to a resistance variable memory element including metal-chalcogen regions within a chalcogenide glass backbone. The metal-chalcogen regions and glass regions bond to form a conducting channel. In addition, a method of operating such memory elements is provided in which metal ions move in and out of the conducting channels in response to applied voltages, thereby affecting the resistance of the memory elements.

1 . A memory element comprising: 
 at least one resistance variable material layer;    at least one metal-containing layer; and    at least one conducting channel formed within said resistance variable material layer, said conducting channel configured to receive and expel metal ions in response to write, erase, and read voltages applied to said memory element.    
     
     
         2 . The memory element of  claim 1 , wherein said resistance variable material layer is a chalcogenide glass layer.  
     
     
         3 . The memory element of  claim 2 , wherein said chalcogenide glass layer has a stoichiometry of Ge x Se 100−x .  
     
     
         4 . The memory element of  claim 3 , wherein said chalcogenide glass layer has a stoichiometry from about Ge 18 Se 82  to Ge 25 Se 75 .  
     
     
         5 . The memory element of  claim 4 , wherein said chalcogenide glass layer is a doped chalcogenide glass layer.  
     
     
         6 . The memory element of  claim 5 , wherein said doped chalcogenide glass layer is doped with metal ions.  
     
     
         7 . The memory element of  claim 6 , wherein said metal ions are silver ions.  
     
     
         8 . The memory element of  claim 7 , wherein said doped chalcogenide glass layer is from about 150 Å to about 600 Å thick.  
     
     
         9 . The memory element of  claim 8 , wherein said doped chalcogenide glass layer has metal-chalcogen regions which are aligned to form said conducting channel.  
     
     
         10 . The memory element of  claim 9 , wherein said metal-chalcogen regions are Ag 2 Se regions within a GeSe glass backbone.  
     
     
         11 . The memory element of  claim 10 , wherein said Ag 2 Se regions become aligned upon application of a conditioning voltage to the memory element.  
     
     
         12 . The memory element of  claim 11 , wherein said conditioning voltage is greater than subsequent write, read, and erase voltages.  
     
     
         13 . The memory element of  claim 12 , wherein the Ag 2 Se regions form at least one conducting channel within the doped chalcogenide glass layer.  
     
     
         14 . The memory element of  claim 11 , wherein prior to application of said conditioning voltage, said memory element has a first resistance state and after application of said conditioning voltage to said memory element, said memory element has a second resistance state lower than said first resistance state.  
     
     
         15 . The memory element of  claim 14 , wherein said write, erase, and read voltages have an absolute magnitude lower than that of said conditioning voltage.  
     
     
         16 . The memory element of  claim 15 , wherein said write voltage produces a third resistance state lower than the second resistance state.  
     
     
         17 . The memory element of  claim 16 , wherein a second write voltage produces a fourth resistance state lower than said third resistance state.  
     
     
         18 . The memory element of  claim 3 , wherein said chalcogenide glass layer has a stoichiometry from about Ge 20 Se 80  to Ge 43 Se 57 .  
     
     
         19 . The memory element of  claim 18 , wherein said chalcogenide glass layer has a stoichiometry of Ge 40 Se 60 .  
     
     
         20 . The memory element of  claim 18 , wherein said chalcogenide glass layer is from about 150 Å to about 500 Å thick.  
     
     
         21 . The memory element of  claim 20 , wherein the at least one metal-containing layer is formed over said chalcogenide glass layer.  
     
     
         22 . The memory element of  claim 21 , wherein said at least one metal-containing layer is from about 300 Å to about 1200 Å thick.  
     
     
         23 . The memory element of  claim 1 , wherein said at least one metal-containing layer is an Ag 2 Se layer.  
     
     
         24 . The memory element of  claim 1 , wherein said resistance variable material has a germanium-selenide glass backbone.  
     
     
         25 . The memory element of  claim 24 , wherein when a conditioning pulse is applied to the memory element, Ag 2 Se is driven into said germanium-selenide glass backbone.  
     
     
         26 . The memory element of  claim 25 , wherein said conditioning pulse has a pulse duration of from about 10 to about 500 ns and greater than about 700 mV.  
     
     
         27 . The memory element of  claim 26 , wherein the Ag 2 Se is bonded to the germanium-selenide glass backbone forming at least one conducting channel within the chalcogenide glass layer.  
     
     
         28 . The memory element of  claim 27 , further comprising a second metal-containing layer formed over the first metal-containing layer.  
     
     
         29 . The memory element of  claim 28 , wherein said second metal-containing layer comprises silver ions.  
     
     
         30 . The memory element of  claim 29 , wherein the silver ions are driven in and out of the at least one conducting channel by applying different voltages.  
     
     
         31 . A memory element comprising: 
 at least one doped chalcogenide glass layer, said doped chalcogenide glass layer comprising polarized metal-chalcogen regions within a glass backbone, wherein said polarized metal-chalcogen regions form at least one conducting channel for receiving and expelling metal ions within said doped chalcogenide glass layer in response to write, erase, and read voltages applied to said memory element, wherein a conditioning voltage is applied that changes said memory element from a first resistance state to a second resistance state, said second resistance state being lower than said first resistance state; and    first and second electrodes electrically coupled to said doped chalcogenide glass layer.    
     
     
         32 - 39 . (canceled)  
     
     
         40 . A memory element comprising: 
 at least one chalcogenide glass layer, said chalcogenide glass layer further comprising bonded regions of metal and glass, wherein said bonded regions of metal and glass form at least one conducting channel within said chalcogenide glass layer;    at least one metal-containing layer formed over said chalcogenide glass layer; and    first and second electrodes electrically coupled to said chalcogenide glass layer.    
     
     
         41 - 119 . (canceled)  
     
     
         120 . A method of operating a memory element comprising a conducting at least one conducting channel formed within a chalcogenide glass material, said method comprising: 
 applying a conditioning voltage to physically align metal-chalcogen regions which form said at least one conducting channel within a chalcogenide glass material, said first voltage moving the memory element from a first to a second resistance state, said first resistance state exhibiting a higher resistance than said second resistance state; and    applying a first write voltage to move metal ions into said conducting channel and placing the memory element in a third resistance state, said third resistance state being lower than said second resistance state.    
     
     
         121 . The method of  claim 120 , further comprising applying a second write voltage to move the memory element into a fourth resistance state, said fourth resistance state being equal to or lower than said third resistance state.  
     
     
         122 . The method of  claim 121 , further comprising applying an erase voltage to move the memory element into a fifth resistance state, said fifth resistance state being higher than said second and third resistance state.  
     
     
         123 - 126 . (canceled)  
     
     
         127 . The method of  claim 120 , wherein the write voltage is less than the conditioning voltage in absolute amplitude.  
     
     
         128 . The method of  claim 121 , wherein the second write voltage is less than or equal to the first write voltage in absolute amplitude.  
     
     
         129 . The method of  claim 122 , wherein the erase voltage is applied with inverse polarity compared to the write voltage.  
     
     
         130 . A method of operating a memory element comprising a chalcogenide glass material with at least one conducting channel formed from bonded metal and glass regions, said method comprising: 
 applying a conditioning voltage to condition the memory element, said first voltage moving the memory element from a first resistance state into a second resistance state, wherein said second resistance state is less than said first resistance state; and    applying a write voltage to move the memory element into a third resistance state, said third resistance state being less than said second resistance state.    
     
     
         131 - 143 . (canceled)