Power dimmer

Abstract

A circuit for controlling the power in a load supplied by an A.C. voltage and directly connected to a first terminal of application of the A.C. voltage, including two isolated-gate bipolar transistors, connected in anti-parallel between a second terminal of application of the A.C. voltage and the load; circuitry for detecting the zero crossing of the A.C. supply voltage in a first direction; circuitry for generating, at each period of the supply voltage, a pulse of predetermined duration for controlling a first one of said transistors, the time of occurrence of the pulse being conditioned by the detection of the zero crossing of the A.C. voltage and by a desired power reference setting a variable delay of occurrence of the pulse with respect to the detected zero crossing; and circuitry for inverting and transferring said pulse to the second transistor.

1 . A circuit for controlling the power in a load supplied by an A.C. voltage and directly connected to a first terminal of application of the A.C. voltage, comprising: 
 two isolated-gate bipolar transistors, connected in anti-parallel between a second terminal of application of the A.C. voltage and the load;    means for detecting the zero crossing of the A.C. supply voltage in a first direction;    means for generating, at each period of the supply voltage, a pulse of predetermined time duration for controlling a first one of said transistors, the time of occurrence of the pulse being conditioned by the detection of the zero crossing of the A.C. voltage and by a desired power reference setting a variable delay of occurrence of the pulse with respect to the detected zero crossing; and    means for inverting and transferring said pulse to the second transistor.    
   
   
       2 . The circuit of  claim 1 , wherein said predetermined duration corresponds to a half-period of the A.C. supply voltage.  
   
   
       3 . The circuit of  claim 1 , wherein said inversion and transfer means comprises an optocoupler.  
   
   
       4 . The circuit of  claim 1 , wherein said generation means comprises a comparator providing a signal for controlling the gate of the first transistor, the turning-off of which is conditioned by said variable delay initialized by said detection circuit.  
   
   
       5 . The circuit of  claim 4 , wherein said variable delay upon turning-off of the first transistor is obtained by a resistive and capacitive cell having its resistance conditioned by a potentiometer and having its charge controlled by said detection circuit.  
   
   
       6 . The circuit of  claim 5 , wherein said pulse of predetermined time duration is obtained by means of said comparator by a resistive and capacitive discharge of the same capacitor as that setting the variable delay.  
   
   
       7 . The circuit of  claim 1 , further comprising a starting circuit.  
   
   
       8 . The circuit of  claim 1  for the control of a resistive and capacitive load, wherein the occurrence of said pulse turns off said first transistor.  
   
   
       9 . The circuit of  claim 1  for the control of a resistive and capacitive load, wherein the occurrence of said pulse turns on said first transistor.