Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby

Abstract

Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, forming a gate insulating layer on the channel regions, and forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.

1 . A method of fabricating a multi-gate transistor comprising: 
 forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed;    forming a gate insulating layer on the channel regions; and    forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.    
   
   
       2 . The method of  claim 1 , wherein forming the patterned gate electrode comprises: 
 forming a conductive layer for a gate electrode on the gate insulating layer conformally to the active pattern;    forming a sacrificial layer for planarizing an upper surface of the substrate by filling a step of the conformally formed conductive layer for the gate electrode; and    forming the gate electrode by patterning the conductive layer and the sacrificial layer.    
   
   
       3 . The method of  claim 2 , wherein forming the sacrificial layer comprises: 
 forming the sacrificial layer on the surface of the resulting structure having the conductive layer; and    filling the step of the conformally formed conductive layer by planarizing the sacrificial layer.    
   
   
       4 . The method of  claim 3 , wherein the sacrificial layer is an amorphous silicon layer.  
   
   
       5 . The method of  claim 3 , wherein planarizing the sacrificial layer includes using a chemical mechanical polishing (CMP) process.  
   
   
       6 . The method of  claim 5 , after forming of the conductive layer, further comprising forming a polishing stop layer on the conductive layer.  
   
   
       7 . The method of  claim 6 , wherein the polishing stop layer is formed of a material selected from the group consisting of SiO 2 , SiN, SiON, and a combination thereof.  
   
   
       8 . The method of  claim 2 , before the patterning of the conductive layer and the sacrificial layer, further comprising: 
 forming an insulating layer on the substrate;    forming a hard mask by patterning the insulating layer using a pattern for defining the gate electrode; and    forming the gate electrode by etching the conductive layer and the sacrificial layer using the hard mask as an etch mask.    
   
   
       9 . The method of  claim 2 , further comprising removing the remaining sacrificial layer after forming the gate electrode.  
   
   
       10 . The method of  claim 9 , wherein the remaining sacrificial layer is removed by a selective wet etching process.  
   
   
       11 . The method of  claim 10 , wherein one of a tetramethylammonium hydroxide (TMAH) solution and a mixed solution of nitric acid, HF and water is used during the selective wet etching process.  
   
   
       12 . The method of  claim 9 , further comprising, before the removing of the sacrificial layer, forming a first spacer on the gate electrode and the lateral surfaces of the sacrificial layer remaining on the gate electrode, wherein in the removing of the sacrificial layer, the first spacer formed on the lateral surface of the sacrificial layer is removed together with the sacrificial layer so that the first spacer remains on the lateral surfaces of the gate electrode.  
   
   
       13 . The method of  claim 12 , wherein the first spacer is formed at a temperature of 550 degrees C. or less.  
   
   
       14 . The method of  claim 13 , wherein the first spacer is formed of a material selected from the group consisting of SiO 2 , SiN, SiON, and a combination thereof.  
   
   
       15 . The method of  claim 12 , after removing the sacrificial layer, further comprising: 
 performing shallow low-concentration ion implantation by implanting ions into the active pattern using the gate electrode and the first spacer as ion-implantation masks;    forming a second spacer on the lateral surfaces of the first spacer; and    performing deep high-concentration ion implantation by implanting ions into the active pattern using the first and second spacers and the gate electrode as ion-implantation masks.    
   
   
       16 . The method of  claim 1 , wherein forming the active pattern comprises: 
 preparing a silicon-on-insulator (SOI) wafer; and    forming the active pattern by patterning a silicon layer of the SOI wafer.    
   
   
       17 . The method of  claim 1 , wherein forming the active pattern includes forming a plurality of active patterns on the substrate, the active patterns having two or more surfaces on which the channel regions are to be formed.  
   
   
       18 . A multi-gate transistor comprising: 
 an active pattern formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed;    a gate insulating layer formed on the active pattern;    a patterned gate electrode formed on the gate insulating layer having a shape conformal to the active pattern; and    a source/drain region formed in the active pattern located in both lateral surfaces of the gate electrode.    
   
   
       19 . The multi-gate transistor of  claim 18 , wherein a height of the gate electrode is in a range of 500-1,000 Å.  
   
   
       20 . The multi-gate transistor of  claim 18 , further comprising a first spacer formed on the lateral surfaces of the gate electrode conformally to the active pattern.  
   
   
       21 . The multi-gate transistor of  claim 20 , wherein the first spacer is formed of a material selected from the group consisting of SiO 2 , SiN, SiON, and a combination thereof.  
   
   
       22 . The multi-gate transistor of  claim 20 , wherein the first spacer has a thickness in a range of 100-200 Å.  
   
   
       23 . The multi-gate transistor of  claim 20 , further comprising a second spacer formed on the lateral surface of the first spacer conformally to the active pattern.  
   
   
       24 . The multi-gate transistor of  claim 23 , wherein the source/drain region comprises a lightly doped drain region aligned with the gate electrode and the first spacer; and 
 a heavily doped region aligned with the second spacer.    
   
   
       25 . The multi-gate transistor of  claim 18 , wherein the active pattern is a patterned silicon layer of an SOI wafer.  
   
   
       26 . The multi-gate transistor of  claim 18 , wherein the active pattern includes a plurality of active patterns having two or more surfaces on which channel regions are to be formed.