Structure and method to improve channel mobility by gate electrode stress modification

Abstract

In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nFET and pFET), carrier mobility is enhanced or otherwise regulated through the reacting the material of the gate electrode with a metal to produce a stressed alloy (preferably CoSi 2 , NiSi, or PdSi) within a transistor gate. In the case of both the nFET and pFET, the inherent stress of the respective alloy results in an opposite stress on the channel of respective transistor. By maintaining opposite stresses in the nFET and pFET alloys or silicides, both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

1 . A method of adjusting carrier mobility in semiconductor devices comprising the steps of 
 depositing a metal or combination of metals to contact one of a first or second transistor gate structure, and    alloying said metal or combination of metals and said one of a first or second transistor gate structure to form a first stressed alloy within said one of a first or second transistor gate structures whereby a first stress is created in at least one corresponding channel of first or second transistors without producing a stress in a channel of the other transistor of said first or second transistors.    
   
   
       2 . A method as recited in  claim 1  in which said alloy is a silicide.  
   
   
       3 . A method as recited in  claim 1  in which first transistor and second transistor are of opposite conductivity types.  
   
   
       4 . A method as recited in  claim 3  comprising further the steps of 
 depositing a metal over said first transistor gate and not over said second transistor gate to alloy with a first electrode to form said first stressed alloy causing a first stress to be applied in at least one channel of said first transistor, and    depositing a metal over said second transistor gate and not over said first transistor gate to alloy with a second electrode to form a second stressed alloy causing a second stress to be applied in at least the channel of said second transistor.    
   
   
       5 . A method as recited in  claim 4  in which said first stressed alloy and second stressed alloy apply opposing stresses.  
   
   
       6 . A method as recited in  claim 5  in which 
 said first stress caused by said first stressed alloy exhibits stress in at least the channel region of said first transistor opposite to the stress provided by said first stressed alloy, and    said second stress caused by said second stressed alloy exhibits stress in at least the channel region of said second transistor opposite to the stress provided by said second stressed alloy.    
   
   
       7 . A method as recited in  claim 6  wherein the carrier mobility is regulated by applying tensile stress to at least one channel of said first transistor while applying compressive stress to at least one channel of said second transistor.  
   
   
       8 - 20 . (canceled)  
   
   
       21 . A method as recited in  claim 1  wherein said metal or combination of metals is selected from the group consisting of Co, Ni and Pd.  
   
   
       22 . A method as recited in  claim 1 , including the further step of alloying a metal or combination of metals in a lower portion of said first or second gate structure to control a work function of said gate material.  
   
   
       23 . A method as recited in  claim 1 , wherein said depositing step includes deposition on at least three sides of an active region of said first or second transistor.