Flip-flop circuit

Abstract

To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a mater latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.

1 . A flip-flop circuit, comprising: 
 an input terminal to which an input signal is input,    a master latch portion for holding a signal input from the input terminal immediately before a timing signal changes from a first state to a second state, while the timing signal is in the second state;    a slave latch portion for holding a signal input from the master latch portion immediately before the timing signal changes from the second state to the first state, while the timing signal is in the first state; and    an output terminal from which a signal according to a signal held in the master latch portion is output when the timing signal is in the second state and a signal according to a signal held in the slave latch portion is output when the timing signal is in the first state,    wherein at least one of an input capacitance at the input terminal and a driving capability at the output terminal when the timing signal is in the first state is equal to that when the timing signal is in the second state.    
   
   
       2 . The flip-flop circuit of  claim 1 , wherein both of the input capacitance at the input terminal and the driving capability at the output terminal when the timing signal is in the first state are equal to those when the timing signal is in the second state.  
   
   
       3 . The flip-flop circuit of  claim 2 , wherein circuit characteristics are extracted as those of a standard cell for use in a cell-base design.  
   
   
       4 . The flip-flop circuit of  claim 2 , further comprising a selecting portion for selecting a signal according to a signal held in the master latch portion when the timing signal is in the second state, selecting a signal according to a signal held in the slave latch portion when the timing signal is in the first state, and causing the selected signal to be output from the output terminal.  
   
   
       5 . The flip-flop circuit of  claim 4 , wherein the selecting portion includes: 
 a first tri-state element for outputting a signal according to a signal held in the master latch portion when the timing signal is in the second state and setting an output thereof in a high-impedance state when the timing signal is in the first state; and    a second tri-state element for outputting a signal according to a signal held in the slave latch portion when the timing signal is in the first state and setting an output thereof in a high-impedance state when the timing signal is in the second state,    wherein the outputs of the first and second tri-state elements are connected to the output terminal, and    a driving capability of the first tri-state element when the timing signal is in the second state is equal to that of the second tri-state element when the timing signal is in the first state.    
   
   
       6 . The flip-flop circuit of  claim 5 , wherein the first and second tri-state elements are tri-state inverters.  
   
   
       7 . The flip-flop circuit of  claim 4 , wherein the selecting portion includes: 
 a first tri-state element for outputting a signal according to a signal held in the master latch portion when the timing signal is in the second state and setting an output thereof in a high-impedance state when the timing signal is in the first state;    a second tri-state element for outputting a signal according to a signal held in the slave latch portion when the timing signal is in the first state and setting an output thereof in a high-impedance state when the timing signal is in the second state; and    a driver for receiving output signals from the first and second tri-state elements and outputting a signal to the output terminal.    
   
   
       8 . The flip-flop circuit of  claim 7 , wherein the first and second tri-state elements are tri-state inverters.  
   
   
       9 . The flip-flop circuit of  claim 7 , wherein the driver is an inverter.  
   
   
       10 . The flip-flop circuit of  claim 4 , wherein the selecting portion includes: 
 a fist pass gate that conducts and outputs a signal according to a signal held in the master latch portion when the timing signal is in the second state, and sets an output thereof in a high-impedance state when the timing signal is in the first state;    a second pass gate that conducts and outputs a signal according to a signal held in the slave latch portion when the timing signal is in the first state, and sets an output thereof in a high-impedance state when the timing signal is in the second state; and    a driver for receiving output signals from the first and second pass gates and outputting a signal to the output terminal.    
   
   
       11 . The flip-flop circuit of  claim 10 , wherein the driver is an inverter.  
   
   
       12 . The flip-flop circuit of  claim 2 , wherein a gate of an identical transistor is electrically connected to the input terminal both when the timing signal is in the first state and when the timing signal is in the second state.  
   
   
       13 . The flip-flop circuit of  claim 2 , wherein the master latch portion is a tri-state element controlled according to the timing signal, and 
 the input terminal is connected to the tri-state element.    
   
   
       14 . The flip-flop circuit of  claim 13 , wherein the tri-state element is a tri-state inverter.  
   
   
       15 . The flip-flop circuit of  claim 1 , wherein at least one of operation of resetting the state of holding a signal according to a reset signal and operation of setting the state of holding a signal according to a set signal is performed.  
   
   
       16 . The flip-flop circuit of  claim 1 , further comprising another input terminal, 
 wherein a signal is held based on a signal input to one of the input terminals, according to a switching control signal.    
   
   
       17 . A flip-flop circuit, comprising: a data input terminal; a data output terminal; a master latch portion; a slave latch portion; a bypass; and a data output selecting portion, 
 wherein the master latch portion includes a first tri-state inverter, a first inverter and a second tri-state inverter,    the first tri-state inverter is in a high-impedance state when a given timing signal is in a first state and outputs an inverted signal of a signal input from the data input terminal when the timing signal is in a second state,    the first inverter outputs an inverted signal of an output of the first tri-state inverter,    the second tri-state inverter is in a high-impedance state when the timing signal is in the second state and outputs an inverted signal of an output of the first inverter to the first inverter when the timing signal is in the first state,    the slave latch portion includes a first pass gate, a second inverter and a third tri-state inverter,    the first pass gate is in a high-impedance state when the timing signal is in the second state and allows an output of the first inverter to pass through when the timing signal is in the first state,    the second inverter outputs an inverted signal of an output of the first pass gate,    the third tri-state inverter is in a high-impedance state when the timing signal is in the first state and outputs an inverted signal of an output of the second inverter to the second inverter when the timing signal is in the second state,    the bypass transmits an output of the first tri-state inverter without change,    the data output selecting portion includes a second pass gate, a third pass gate and a third inverter,    the second pass gate is in a high-impedance state when the timing signal is in the first state and allows an output of the second inverter to pass through when the timing signal is in the second state,    the third pass gate is in a high-impedance state when the timing signal is in the second state and allows an output of the first tri-state inverter to pass through when the timing signal is in the first state, and    the third inverter receives outputs of the second and third pass gates and outputs an inverted signal of each of the outputs to the data output terminal.    
   
   
       18 . The flip-flop circuit of  claim 17 , wherein the first tri-state inverter is a tri-state selector that is in a high-impedance state when the timing signal is in the first state and outputs, according to a given selection signal, an inverted signal of a signal input from the data input terminal or another data input terminal when the timing signal is in the second state.  
   
   
       19 . The flip-flop circuit of  claim 18 , wherein the second tri-state inverter is a tri-state logic gate element that is in a high-impedance state when the timing signal is in the second state and outputs, according to a given reset signal, an inverted signal of an output of the first inverter or a signal at a level enough to set the master latch portion in a reset state to the first inverter when the timing signal is in the first state, and 
 the second inverter is a logic gate element that outputs, according to the reset signal, an inverted signal of an output of the first pass gate or a signal at a level enough to set the slave latch portion in a reset state.    
   
   
       20 . The flip-flop circuit of  claim 18 , wherein the first inverter is a logic gate element that outputs, according to a given set signal, an inverted signal of an output of the tri-state selector or a signal at a level enough to set the master latch portion in a set state, and 
 the third tri-state inverter is a tri-state logic gate element that is in a high-impedance state when the timing signal is in the first state and outputs, according to the set signal, outputs an inverted signal of an output of the second inverter or a signal at a level enough to set the slave latch portion in a set state to the second inverter when the timing signal is in the second state.