Test mode decoder in a flash memory

Abstract

Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

1 . An integrated circuit fabrication method, comprising: 
 forming a dielectric layer on a substrate;    forming a control gate in the dielectric layer;    forming a metal, first line on the dielectric material such that the first line is spaced from the control gate by a dimension;    forming a conductive, second line on the dielectric material such that the second line is spaced from the control gate by the dimension; and    forming a signal connection between the control gate and the first line.    
   
   
       2 . The method of  claim 1 , wherein forming a dielectric layer on a substrate comprises forming a silicon dioxide layer on a silicon substrate.  
   
   
       3 . The method of  claim 2 , wherein forming a control gate in the dielectric layer includes forming a doped polysilicon gate in the silicon dioxide layer, forming a first metal layer in the silicon dioxide layer, and forming a contact between the doped polysilicon gate and the first metal layer to couple a signal from the first metal layer to the doped polysilicon gate.  
   
   
       4 . The method of  claim 3 , wherein forming the signal connection includes forming a via having the dimension and filling the via with a metal.  
   
   
       5 . The method of  claim 4 , wherein forming the silicon dioxide layer includes separating the first metal line from the second metal line.  
   
   
       6 . A method of fabricating an integrated circuit, comprising: 
 forming a dielectric layer on a substrate;    forming a control gate in the dielectric layer;    forming a conductive, first line formed on the dielectric material layer above the control gate and separated from the control gate by a thickness of the dielectric layer;    forming a conductive, second line on the dielectric material layer above the control gate and separated from the control gate by the thickness of the dielectric layer; and    forming a signal connection in a via extending between and in contact with the control gate and one of the first line and the second line to couple signals between the control gate and the one of the first line and the second line, the via having a dimension substantially the same as the thickness of the dielectric layer.    
   
   
       7 . The method of  claim 6 , wherein forming a dielectric layer on a substrate comprises forming a silicon dioxide layer on a silicon substrate.  
   
   
       8 . The method of  claim 6 , wherein forming a control gate comprises: 
 forming a doped polysilicon gate in the dielectric layer;    forming a metal gate in the dielectric layer; and    forming a contact between the doped polysilicon gate and the metal gate.    
   
   
       9 . The method of  claim 6 , wherein forming the signal connection includes forming a via in the dielectric layer and inserting a metal in the via.  
   
   
       10 . The method of  claim 6 , wherein forming a dielectric layer includes electrically separating the first line and the second line.  
   
   
       11 . The method of  claim 6 , wherein the dimension of the via is a height dimension extending vertically from the substrate.  
   
   
       12 . The method of  claim 11 , wherein forming the signal connection in the via includes selectively placing the via during fabrication based on the required test commands to be decoded by the integrated circuit.  
   
   
       13 . The method of  claim 12 , wherein forming the first line comprises coupling the first line to a first one of an inverted data line and a non-inverted data line, and wherein forming the second line comprises coupling the second line to a second one of an inverted data line and a non-inverted data line.  
   
   
       14 . A method of operating a memory device, comprising: 
 storing control parameters for a memory device in a non-volatile data storage unit in response to receiving a test mode signal;    operating the memory device using the stored control parameters to adjust the operation of the memory device, including;    writing data to a selected one memory cell of a plurality of memory cells forming the memory device by holding a source of the memory cell at a reference voltage, holding a drain of the memory cell at a power voltage, and applying a high power voltage to a gate of the memory cell for a first predetermined time period;    reading data stored in the selected one memory cell by holding the source at the reference voltage, holding the drain at a low power voltage, and applying the power voltage to the gate for a second predetermined time period;    erasing data store in the selected one memory cell by holding the source to the high voltage level for a third predetermined time period, disconnecting the drain from voltage sources, and holding the gate to the reference voltage.    
   
   
       15 . The method of  claim 14 , wherein receiving the test mode signal includes receiving a test mode signal pulse at a voltage level higher than signal voltages present in the memory device.  
   
   
       16 . The method of  claim 15 , wherein receiving the test mode signal includes at least one of a reset/power down signal and a write enable signal.  
   
   
       17 . The method of  claim 15 , wherein receiving the test mode signal includes detecting the voltage level of a reset/power down signal with a high voltage detector before receiving the signal at a command user interface.  
   
   
       18 . The method of  claim 15 , wherein receiving the test mode signal includes detecting a super voltage level of the reset/power down signal, detecting a first coincident write enable pulse during the super voltage level and a first command signal, and detecting a second coincident enable pulse during the super voltage level and a second command signal; 
 placing the memory device in a test mode in response to the super voltage, the first command signal and the second command signal.    
   
   
       19 . The method of  claim 18 , wherein placing the memory device in test mode includes generating a test mode clock signal, receiving a plurality of test mode command signals on a plurality of test mode input data lines, and decoding the plurality of test mode command signals.  
   
   
       20 . The method of  claim 14 , wherein the reference voltage level is approximately ground, the low power voltage is about 1.0 volts, the power voltage is from about 5 to 7 volts, and the high power voltage is from 10 to 12 volts.  
   
   
       21 . The method of  claim 18 , wherein the test mode command signals include at least one of: 
 reference voltage level, low power voltage level, power voltage level, high power voltage level, the length of time of the first, second and third predetermined time periods;    the magnitude and duration of programming pulses, read pulses, write pulses, erase pulses and heal pulses;    the word length of information stored in the plurality of memory cells forming the memory device;    top addressing and bottom addressing the information stored in the plurality of memory cells forming the memory device; and    the configuration of the plurality of memory cells forming the memory device.    
   
   
       22 . A method of operating a memory device, comprising: 
 storing control parameters for a memory device in a non-volatile data storage unit in response to receiving a test mode signal;    operating the memory device using the stored control parameters to adjust the operation of the memory device;    receiving a plurality of test command signals on a plurality of input data lines after receiving the test mode signal;    decoding the test command signals during a first pulse of a test mode clock signal;    wherein receiving the test mode signal includes: 
 receiving a super voltage signal on a reset signal line;  
 receiving at least one write enable signal during a duration of the super voltage signal on the reset line;  
 receiving a first command during a first write enable pulse, and decoding the first command;  
 receiving a second command during a second write enable pulse, and decoding the second command; and  
 determining if the first and second command constitute a test mode signal.  
   
   
   
       23 . The method of  claim 22 , wherein the test mode clock signal is coincident with at least one of the at least one write enable signals.  
   
   
       24 . The method of  claim 22 , wherein decoding the test command signals includes: 
 coupling the test command signals on the plurality of input data lines after receiving the test mode signal to a plurality of non-inverting data lines to be non-inverted test command signals;    inverting the test command signals to generate a plurality of inverted test command signals and coupling to a plurality of inverted data lines;    coupling a voltage source through a p-channel transistor to a line connected to a plurality of source/drain diffuision regions of a first n-channel transistor, seven middle n-channel transistors and a last n-channel transistor, wherein all the n-channel transistors are coupled in a series of connected source/drain diffusion regions;    coupling the test mode clock signal to a gate region of the first n-channel transistor; and    coupling a selected one of the inverted or non-inverted test command signals to a selected one of the seven middle n-channel transistors and the last n-channel transistor forming a unique pattern of test command signals that will switch on all of the seven middle n-channel transistors and the last n-channel transistor to decode the command signal.    
   
   
       25 . The method of  claim 24 , wherein switching on all of the seven middle n-channel transistors and the last n-channel transistor to decode the command signal includes setting one of a latch and a non-volatile memory cell to a preselected state to indicate that the test command signal has been decoded.  
   
   
       26 . The method of  claim 25 , wherein the memory device exchanges signals with at least one of a processor, a memory controller, a display unit, a user interface, a bus, and an input/output system.  
   
   
       27 . The method of  claim 26 , wherein the signals exchanged include at least one of an address signal, a data signal, a chip enable signal, a write protect signal, a refresh signal, a heal signal, an erase signal, a program signal, and output enable signal, a write enable signal, and a status signal.  
   
   
       28 . The method of  claim 27 , wherein the signals are exchanged between devices embedded on the same integrated circuit chip as the memory device.  
   
   
       29 . The method of  claim 24 , wherein the device comprises more n-channel devices than p-channel devices.