Integrated test circuit

Abstract

A test cell ( 12 ) provides boundary scan testing in an integrated circuit ( 10 ). The test cell ( 12 ) comprises two memories, a flip-flop ( 24 ) and a latch ( 26 ), for storing test data. A first multiplexer ( 22 ) selectively connects one of a plurality of inputs to the flip-flop ( 24 ). The input of the latch ( 26 ) is connected to output of the flip-flop ( 24 ). The output of the latch ( 26 ) is connected to one input of a multiplexer ( 28 ), the second input to the multiplexer ( 28 ) being a data input (DIN) signal. A control bus ( 17 ) is provided for controlling the multiplexers ( 22, 28 ), flip-flop ( 24 ) and latch ( 26 ). The test cell allows input data to be observed and output data to be controlled simultaneously.

1 . A boundary scan test cell for use in conjunction with an integrated circuit containing application logic circuitry comprising: 
 a first memory for storing serial data and transmitting said serial data to other test cells; and    a second memory connected to said first memory for storing output data.    
   
   
       2 . The test cell of  claim 1  and further comprising circuitry connecting said second memory to the application logic.  
   
   
       3 . The test cell of  claim 1  and further comprising circuitry to connect the output of said second memory to the input of the first memory.  
   
   
       4 . The test cell of  claim 1  and further comprising hold circuitry to maintain the output of said second memory at a given state.  
   
   
       5 . The test cell of  claim 1  and further comprising toggle circuitry to alternate the output of said second memory between first and second logic levels.  
   
   
       6 . The test cell of  claim 1  wherein the output of said first memory is connected to the output of said second memory such that said second memory can be loaded with a predetermined logic value.  
   
   
       7 . The test cell of  claim 1  and further comprising circuitry to connect said first memory to an input of the integrated circuit.  
   
   
       8 . The test cell of  claim 1  and further comprising circuitry to connect said second memory to an output of the integrated circuit.  
   
   
       9 . A boundary scan test cell comprising: 
 a first memory;    a first multiplexer for connecting one of a plurality of inputs to said first memory responsive to a first control signal;    a second memory connected to the output of said first memory; and    a second multiplexer for selecting an output from one of a set of inputs to the second multiplexer including the output of said second memory responsive to a second control signal.    
   
   
       10 . The test cell of  claim 9  wherein said first memory comprises a D-type flip-flop.  
   
   
       11 . The test cell of  claim 10  and further comprising clock circuitry for producing a clock signal connected to said D-type flip-flop, such that the output of said first multiplexer is stored in said first memory at each clock pulse.  
   
   
       12 . The test cell of  claim 9  wherein said second memory comprises a D-type latch.  
   
   
       13 . The test cell of  claim 12  and further comprising control circuitry connected to said latch for producing a hold signal responsive to which said latch stores data output from said first memory.  
   
   
       14 . The test cell of  claim 9  wherein said second memory includes inverted and non-inverted outputs, said inverted output connected as one of said inputs to said first multiplexer, such that a toggled output may be produced by the test cell.  
   
   
       15 . The test cell of  claim 9  wherein the output of said first memory is connected as one of said inputs to first multiplexer.  
   
   
       16 . An integrated circuit having boundary scan testing, comprising: 
 application logic circuitry having one or more inputs and one or more outputs;    one or more data inputs for receiving data into the integrated circuit;    one or more data outputs for outputting data from the integrated circuit;    a test data input for receiving test data into the integrated circuit;    one or more input test cells connected between respective data inputs and said application logic circuitry, said input test cells comprising: 
 a first memory for storing serial data; and  
 a second memory connected to said first memory for storing output data.