Structure and method to preserve STI during etching

Abstract

Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

1 - 17 . (canceled)  
   
   
       18 . A semiconductor device, comprising a semiconductor substrate comprising a plurality of active silicon areas separated by a STI (shallow trench isolation) layer wherein said STI layer is covered by a protective capping layer of silicon nitride.  
   
   
       19 . A semiconductor structure comprising: 
 a plurality of active areas separated by one or more shallow trench isolations;    said active areas and shallow trench isolations covered by a layer of silicon nitride, wherein said layer of silicon nitride comprises depressions over said shallow trench isolations; and    a protective film disposed in said depressions.    
   
   
       20 . (canceled)  
   
   
       21 . The device of  claim 18 , wherein the STI layer is formed of an oxide.  
   
   
       22 . The device of  claim 18 , wherein the protective capping layer is formed of silicon nitride.  
   
   
       23 . The device of  claim 18 , wherein an upper surface of the STI layer is recessed below an upper surface of the active silicon areas.  
   
   
       24 . The device of  claim 23 , wherein the protective capping layer is formed on said upper surface of the STI layer and covers sidewalls of the active silicon areas adjacent the recessed surface of the STI layer.  
   
   
       25 . The device of  claim 18 , further comprising a lining layer formed between the STI layer and the protective capping layer.  
   
   
       26 . The device of  claim 18 , wherein the semiconductor substrate is a SOI (silicon on insulator) substrate.  
   
   
       27 . The device of  claim 26 , wherein the SOI substrate comprises a buried oxide layer below the active silicon areas and wherein the STI layer is formed down to the buried oxide layer.  
   
   
       28 . A semiconductor device, comprising: 
 a semiconductor substrate comprising plurality of active silicon areas separated by a STI (shallow trench isolation) layer, wherein an upper surface of the STI layer is recessed below an upper surface of the active silicon areas; and    a conformal capping layer formed over the semiconductor substrate such that a depression is formed in a region of the conformal capping layer disposed over the STI layer; and    a protective film formed in said depression.    
   
   
       29 . The device of  claim 28 , wherein the STI layer is formed of an oxide.  
   
   
       30 . The device of  claim 28 , wherein the conformal capping layer is formed of silicon nitride.  
   
   
       31 . The device of  claim 28 , further comprising a conformal lining layer formed between the semiconductor substrate and the conformal capping layer.  
   
   
       32 . The device of  claim 28 , wherein the semiconductor substrate is a SOI (silicon on insulator) substrate.  
   
   
       33 . The device of  claim 32 , wherein the SOI substrate comprises a buried oxide layer below the active silicon areas and wherein the STI layer is formed down to the buried oxide layer.