Method for enhancing field oxide and integrated circuit with enhanced field oxide

Abstract

A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1 - 60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4 - 50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions. In addition, the poly tiles themselves increase the thickness of the isolation between active silicon regions when it must serve as a self-aligned blocking layer for an ion implantation step.

1 . An integrated circuit comprising: 
 a semiconductor substrate;    a plurality of active regions in a surface of the substrate;    a plurality of surface insulating regions formed in the substrate and from the semiconductor material of the substrate for electrically isolating active regions from each other;    protection tiles over the surface insulating regions for protecting the surface isolating regions from size reduction or increasing the effective thickness of the insulating region.    
   
   
       2 . The integrated circuit of  claim 1  wherein the protection tiles are on the insulating regions and comprise polysilicon.  
   
   
       3 . The integrated circuit of  claim 2  further comprising insulated polysilicon gates wherein the polysilicon in the gates and the polysilicon of the protection tiles are formed from the same layer of polysilicon.  
   
   
       4 . The integrated circuit of  claim 3  wherein the polysilicon in the protection tiles is separated from the polysilicon in the gates.  
   
   
       5 . The integrated circuit of  claim 1  wherein breakdown voltage of regions adjacent LOCOS protection tiles is greater than breakdown voltage of a corresponding region in an integrated circuit without LOCOS protection tiles.  
   
   
       6 . The integrated circuit of  claim 1  wherein the LOCOS protection tile electrically floats.  
   
   
       7 . The integrated circuit of  claim 1  wherein for active area spaces less than of equal to 0.6 microns, the LOCOS protection tiles are generated 0.15 microns from the edges of the active areas.  
   
   
       8 . The integrated circuit of  claim 1  wherein for active area spaces greater than 0.6 microns and less than 1.0 microns, the LOCOS protection tiles are generated 0.20 microns from the edges of the active areas.  
   
   
       9 . An integrated circuit comprising: 
 a monocrystalline silicon substrate;    a plurality of active regions in a surface of the substrate;    a plurality of field oxide regions in the surface, formed from the silicon substrate and electrically isolating active regions from each other.    a layer of polysilicon over the field oxide regions for protecting the field oxide regions from erosion or increasing the effective thickness of the insulating region.    
   
   
       10 . The integrated circuit of  claim 9  further comprising active metal oxide semiconductor regions, polysilicon gates disposed over the active metal oxide semiconductor regions and the polysilicon in the gates and the polysilicon over the field oxide regions are formed from a common layer of polysilicon.  
   
   
       11 . The integrated circuit of  claim 9  wherein breakdown voltage of regions on opposite sides of the LOCOS with protection tiles is greater than the breakdown voltage of a corresponding region in an integrated circuit made without LOCOS protection tiles.  
   
   
       12 . The integrated circuit of  claim 9  wherein the LOCOS protection tile electrically floats.  
   
   
       13 . The integrated circuit of  claim 9  wherein for active area spaces less than of equal to 0.6 microns, the LOCOS protection tile is generated 0.15 microns from the edges of the active areas.  
   
   
       14 . The integrated circuit of  claim 9  wherein for active area spaces greater than 0.6 microns and less than 1.0 microns, the LOCOS protection tile is generated 0.20 microns from the edges of the active areas.  
   
   
       15 . An integrated circuit comprising: 
 a monocrystalline silicon substrate;    a plurality of active regions in a surface of the substrate;    a plurality of field oxide regions in the surface, formed from the silicon substrate and electrically isolating active regions from each other;    polysilicon tiles on the field oxide regions.    
   
   
       16 . The integrated circuit of  claim 15  further comprising active metal oxide semiconductor regions, polysilicon gates disposed between the active metal oxide semiconductor regions and the polysilicon in the gates and the polysilicon on the field oxide regions are formed from a common layer of polysilicon.  
   
   
       17 . The integrated circuit of  claim 15  wherein breakdown voltage of regions on opposite sides of the LOCOS protection tiles is greater than breakdown voltage of corresponding regions in integrated circuits made without LOCOS protection tiles.  
   
   
       18 . The integrated circuit of  claim 15  wherein the LOCOS protection tile electrically floats.  
   
   
       19 . The integrated circuit of  claim 15  wherein for active area spaces less than or equal to 0.6 microns, the LOCOS protection tile is generated 0.15 microns from the edges of the active areas.  
   
   
       20 . The integrated circuit of  claim 15  wherein for active area spaces greater than 0.6 microns and less than 1.0 microns, the LOCOS protection tile is generated 0.20 microns from the edges of the active areas.  
   
   
       21 . A process for fabricating a metal oxide integrated circuit comprising the steps of: 
 providing a substrate of monocrystalline silicon;    depositing a layer of silicon nitride over the substrate;    forming openings in the silicon nitride layer to expose surface regions for local oxidation;    locally oxidizing the exposed surface regions of the silicon substrate to form regions of local oxide (LOCOS);    removing the rest of the silicon nitride layer to expose surface regions of the silicon substrate between the LOCOS regions;    oxidizing the exposed surface regions of the silicon substrate to form a gate oxide layer on the silicon substrate;    depositing a polysilicon layer over the surface of the substrate;    patterning the polysilicon layer to simultaneously form polysilicon gates and LOCOS protection tiles; and    implanting the substrate to form active regions in the semiconductor substrate.    
   
   
       22 . The process of  claim 21  comprising the further step of removing the gate oxide layer from active regions.  
   
   
       23 . The process of  claim 21  wherein the step of implanting the active areas occurs after formation of the LOCOS protection tiles.  
   
   
       24 . The process of  claim 21  wherein the active regions comprise source regions on one side of the gates and drain regions on the other side of the gates.  
   
   
       25 . The process of  claim 21  wherein the active regions comprise source regions on both sides of the gates.  
   
   
       26 . The process of  claim 25  further comprising forming a drain region on the opposite side of the semiconductor substrate.  
   
   
       27 . The process of  claim 21  further comprising the steps of depositing other insulating or conductive layers over the substrate and patterning and removing unwanted portions of those layers and leaving the LOCOS protection tiles in place to prevent reduction of the size of the LOCOS regions during such further steps.  
   
   
       28 . The process of  claim 21  wherein the thickness of the LOCOS regions remains substantially the same during subsequent process steps.  
   
   
       29 . The process of  claim 21  wherein breakdown voltage of a device with LOCOS protection tiles is greater than a corresponding device made with the same process steps but without LOCOS protection tiles.  
   
   
       30 . The process of  claim 21  wherein the LOCOS protection tile electrically floats.  
   
   
       31 . The process of  claim 21  wherein for active area spaces less than of equal to 0.6 microns, the LOCOS protection tile is generated 0.15 microns from the edges of the active areas.  
   
   
       32 . The process of  claim 21  wherein for active area spaces greater than 0.6 microns and less than 1.0 microns, the LOCOS protection tile is generated 0.20 microns from the edges of the active areas.