Semiconductor devices with high voltage tolerance

Abstract

The present invention provides improve device designs for high voltage tolerance and methods for making the same. In one embodiment, a low doped drain extension (LDD) region is extended to sustain higher voltages with minimal extra space and processing. In another example, a trench isolation barrier is placed between the gate and an active region in a well. In another example, an additional trench isolation barrier is placed under the middle of the gate. The trench is filled with dielectric such as oxides, with a small upper portion replaced with recrystallized silicon. These disclosed transistor devices can have parameters controlled so that predetermined performances of the transistor devices can be achieved.

1 . A high voltage transistor comprising: 
 a first active region on a first side of a gate in a substrate;    a second active region on a second side of the gate in the substrate;    a first low doped region formed between the gate and the first active region; and    a second low doped region formed between the gate and the second active region with a length substantially longer than that of the first low doped region.    
   
   
       2 . The transistor of  claim 1  the second active region is a drain of the transistor.  
   
   
       3 . The transistor of  claim 1  wherein the first low doped region is substantially under the gate and a spacer on the first side of the gate, while the second low doped region is partially under the gate and a spacer on the second side of the gate.  
   
   
       4 . The transistor of  claim 1  wherein the second low doped region is at least 0.2 um longer than the first low doped region.  
   
   
       5 . The transistor of  claim 1  wherein the first low doped region has a lateral length less than about 0.3 um.  
   
   
       6 . The transistor of  claim 1  wherein the second low doped region has a lateral length less than about 0.7 um.  
   
   
       7 . A high voltage transistor comprising: 
 a first active region formed on a first side of a gate and in a well of a predetermined type within a substrate;    a second active region on a second side of the gate; and    a trench isolation (TI) of a predetermined depth formed within the well between the first active region and the gate,    wherein the well containing the first active region functions as a drain of the transistor.    
   
   
       8 . The transistor of  claim 7  wherein the well is an N well if the transistor is an NMOS transistor.  
   
   
       9 . The transistor of  claim 7  wherein the well is a P well if the transistor is a PMOS transistor.  
   
   
       10 . The transistor of  claim 7  wherein a performance of the transistor is determined by a distance (d 1 ) between an edge of the gate to an edge of the first active region, which affects a drain resistance.  
   
   
       11 . The transistor of  claim 10  wherein the drain resistance is further affected by an electron or hole concentration of the well.  
   
   
       12 . The transistor of  claim 10  wherein the performance of the transistor is further affected by a distance (d 2 ) between an edge of the gate in the well and the edge of the channel outside of the well.  
   
   
       13 . The transistor of  claim 12  wherein a channel length of the transistor is larger than d 2 .  
   
   
       14 . A semiconductor transistor comprising: 
 a gate;    a source region formed in a substrate on a first side of the gate;    a drain region formed in the substrate on a second side of the gate; and    a trench isolation placed in the substrate between the source and drain regions underneath the gate with a predetermined top portion thereof forming a portion of a channel between the source and drain region.    
   
   
       15 . The transistor of  claim 14  wherein the top portion of the trench isolation includes a crystallized silicon material.  
   
   
       16 . The transistor of  claim 14  further comprising a first and second shallow trench isolations (STI) on the first and second sides of the gate respectively for defining a boundary of the transistor.  
   
   
       17 . The transistor of  claim 14  further comprising a first and second low doped drain extension regions overlapping at least a portion of the drain and source regions respectively.  
   
   
       18 . A method for forming a transistor comprising: 
 forming at least three trenches in a substrate with a center trench surrounded by two boundary trenches;    filling the three trenches with a predetermined dielectric material;    placing a predetermined silicon material in a predetermined top portion of the center trench;    crystallizing the placed silicon material;    forming a gate over the substrate and substantially centered around the center trench; and    forming a source and a drain regions on both sides of the gate and next to the respective boundary trench.    
   
   
       19 . The method of  claim 18  wherein the placing further includes removing the dielectric material from the predetermined top portion of the center trench.  
   
   
       20 . The method of  claim 18  further comprising forming a first and second low doped drain extension regions overlapping at least a portion of the drain and source regions respectively.  
   
   
       21 . The method of  claim 18  further wherein forming the gate comprising forming two spacers on two sides of the gate.  
   
   
       22 . The method of  claim 18  further comprising forming a well around the three trenches.