Semiconductor device and method of manufacturing same

Abstract

A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3 a being adjacent to the channel region and a second part 3 b formed to protrude in a channel width direction from the first part 3 a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3 b for connecting the source/drain regions 2 to source/drain wirings.

1 - 11 . (canceled)  
   
   
       12 . A semiconductor device comprising: 
 a substrate;    a transistor having a pair of source/drain regions formed in said substrate, a gate electrode formed via a gate dielectric film on a channel region sandwiched between said pair of source/drain regions, and a side wall formed on a side surface of said gate electrode;    an interlayer dielectric film formed on said transistor;    source/drain wirings formed on said interlayer dielectric film; and    conductors formed in said interlayer dielectric film for connecting said source/drain wirings to said source/drain regions, wherein    said side wall is constructed with a porous material having voids and organic particles.    
   
   
       13 . (canceled)