Semiconductor device

Abstract

A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions ( 11 ) are formed after a silicon layer ( 3 ) has been thinned through formation of recesses ( 14 ). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer ( 3 ) that are located between the bottoms of element isolation insulating films ( 5 ) and the top surface of a BOX layer ( 2 ), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions ( 11 ) are formed to reach the upper surface of the BOX layer ( 2 ), the junction capacitance of source/drain regions ( 12 ) is not increased.

1 - 2 . (canceled)  
   
   
       3 . A semiconductor device comprising: 
 an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;    element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;    a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;    a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and    source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,    wherein the edge region of each said recess reaches under the edge region of said gate structure.    
   
   
       4 - 8 . (canceled)  
   
   
       9 . A semiconductor device comprising: 
 an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;    element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;    a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;    a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses;    source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer;    semiconductor regions formed on the bottom surfaces of said recesses; and    metal-semiconductor compound layers formed on said semiconductor regions,    wherein the part of said main surface of said semiconductor layer on which said gate structure resides forms an angle larger than 90° with a corresponding side surface of each said recess.    
   
   
       10 . A semiconductor device comprising: 
 an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;    element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;    a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;    a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and    source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,    wherein said SOI substrate comprises an NMOS transistor and a PMOS transistor that are formed therein, and    said semiconductor device is only one of said NMOS transistor and said PMOS transistor.    
   
   
       11 . A semiconductor device comprising: 
 an SOI substrate having a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type that are stacked in this order;    element isolation insulating films formed partially in a main surface of said semiconductor layer, with portions of said semiconductor layer interposed between said insulating layer and bottom surfaces of said element isolation insulating films;    a gate structure formed partially on said main surface of said semiconductor layer in an element formation region defined by said element isolation insulating films;    a pair of recesses formed in said element formation region, said recesses being formed in said main surface of said semiconductor layer in portions that are not covered by said gate structure, with a channel formation region under said gate structure interposed between said pair of recesses; and    source/drain regions formed in bottom surfaces of said recesses and having a second conductivity type that is different from said first conductivity type, said source/drain regions forming a pair, with said channel formation region interposed therebetween, and having bottom surfaces or depletion layers that reach said insulating layer,    wherein said SOI substrate comprises a first transistor operating at a relatively low power-supply voltage and a second transistor operating at a relatively high power-supply voltage; and    said semiconductor device is only one of said first transistor and said second transistor.