Integration method of a semiconductor device having a recessed gate electrode

Abstract

Embodiments of the invention are directed to an integrated circuit device and a method for forming the device. In some embodiments of the invention, two types of transistors are formed on a single substrate, transistors: transistors having a recessed gate, and transistors having a planer gate electrode. In other embodiments, transistors having a recessed gate are formed in multiple areas of the same substrate. Additionally, gates of the transistors in more than one region may be formed simultaneously.

1 . A memory device, comprising: 
 a substrate divided into a memory cell region and a peripheral circuit region;    a plurality of memory cells having recessed gates formed in the memory cell region; and    at least one transistor in the peripheral circuit region, the transistor including: 
 a channel region formed between a source region and a drain region,  
 a gate structure disposed over the channel region, and  
 a resistance-reducing layer formed over the source and drain regions.  
   
   
   
       2 . The memory device of  claim 1  wherein the resistance-reducing layer comprises Cobalt.  
   
   
       3 . The memory device of  claim 2  wherein the resistance-reducing layer comprises a Cobalt-Silicon material.  
   
   
       4 . The memory device of  claim 1 , further comprising an epitaxially grown silicon structure disposed between the source and drain regions and the resistance-reducing layer.  
   
   
       5 . The memory device of  claim 4  wherein the epitaxially grown silicon structure is formed by SEG (Selective Epitaxial Growing).  
   
   
       6 . A memory device comprising: 
 a substrate divided into a cell region and a peripheral region;    a plurality of memory cells formed in the cell region, the plurality of memory cells each having a recessed gate structure; and    a plurality of transistors in the peripheral region, the plurality of transistors each having a recessed gate structure.    
   
   
       7 . The memory device of  claim 6  wherein gates of the memory cells in the cell region and gates of the cells in the peripheral region are formed simultaneously.