NROM flash memory with a high-permittivity gate dielectric

Abstract

A high permittivity gate dielectric is used in an NROM memory cell. The gate dielectric has a dielectric constant greater than silicon dioxide and is comprised of an atomic layer deposited and/or evaporated nanolaminate structure. The NROM memory cell has a substrate with doped source/drain regions. The high-k gate dielectric is formed above the substrate between a pair of the source/drain regions. A polysilicon control gate is formed on top of the gate dielectric. The gate dielectric can have an oxide—high-k dielectric—oxide composite structure, an oxide—nitride—high-k dielectric composite structure, or a high-k dielectric—high-k dielectric—high-k dielectric composite structure.

1 . An NROM memory transistor comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;    a composite gate insulator layer formed on top of the substrate and substantially between the plurality of source/drain regions, the gate insulator comprises a composition of high-k—high-k—high-k dielectric layers of one of: HfO 2 —Ta 2 O 5 —HfO 2  or HfO 2 —ZrO 2 —HfO 2 ; and    a control gate formed on top of the gate insulator layer.    
   
   
       2 . The transistor of  claim 1  wherein the plurality of source/drain regions are comprised of an n+ type doped silicon.  
   
   
       3 . The transistor of  claim 1  wherein the control gate is a polysilicon material.  
   
   
       4 . The transistor of  claim 1  wherein the substrate is comprised of a p-type silicon material.  
   
   
       5 . The transistor of  claim 1  wherein one of metal layers Ta 2 O 5  or ZrO 2  acts as a charge trapping layer.  
   
   
       6 . The transistor of  claim 5  wherein the charge trapping layer comprises a metal that has a lower conduction band edge than silicon nitride.  
   
   
       7 . The transistor of  claim 1  wherein the composite gate insulator is comprised of one of: atomic layer deposited (ALD) La 2 O 3 —ALD HfO 2 —ALD La 2 O 3 , ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—ALD ZrO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide, ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—ALD HfO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide, or ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—evaporated HfO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide.  
   
   
       8 . The transistor of  claim 1  wherein the composite gate insulator layer is formed by atomic layer deposition.  
   
   
       9 . An electronic system comprising: 
 a processor that generates control signals; and    a memory array coupled to the processor, the array comprising a plurality of NROM memory cells, each NROM memory cell comprising: 
 a substrate having a pair of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;  
 a nanolaminate gate dielectric formed on top of the substrate substantially between each pair of the source/drain regions, the gate dielectric comprises a composition of high-k—high-k—high-k dielectric layers of one of: atomic layer deposited (ALD) HfO 2 —ALD Ta 2 O 5 —ALD HfO 2  or ALD HfO 2 —ALD ZrO 2 —ALD HfO 2 ; and  
 a control gate formed on top of the oxide insulator.  
   
   
   
       10 . The system of  claim 9  wherein the memory array is part of a memory device that is coupled to the processor through an address bus, a data bus, and a control bus.  
   
   
       11 . The system of  claim 9  and further including address circuitry coupled to row and column decoders that generate signals for accessing memory cells of the memory array.  
   
   
       12 . The system of  claim 9  wherein the pair of source/drain regions are n+ doped regions wherein each region can act as either a source region or a drain region.  
   
   
       13 . A memory device comprising a plurality of NROM memory transistors fabricated on a substrate, each transistor comprising: 
 a pair of source/drain regions having a different conductivity than the remainder of the substrate;    a composite gate insulator layer formed on top of the substrate and substantially between the plurality of source/drain regions, the gate insulator comprises a composition of high-k—high-k—high-k dielectric layers of one of: atomic layer deposition (ALD) La 2 O 3 —ALD HfO 2 —ALD La 2 O 3 , ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—ALD ZrO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide, ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—ALD HfO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide, or ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide—evaporated HfO 2 —ALD Lanthanide (Pr, Ne, Sm, Gd, and Dy) Oxide; and    a control gate formed on top of the gate insulator layer.    
   
   
       14 . The memory device of  claim 13  wherein the pair of source/drain regions are n+ doped regions in a p-type silicon substrate.  
   
   
       15 . The memory device of  claim 13  wherein the composite gate insulator is comprised of a composition such that barriers between the substrate and the gate insulator are reduced.  
   
   
       16 . The memory device of  claim 13  wherein the composite gate insulator is comprised of a floating gate layer such that an energy barrier between the floating gate layer and the remainder of the gate insulator are reduced.  
   
   
       17 . The memory device of  claim 16  wherein tunneling current increases in response to the floating gate layers of either HfO 2  or ZrO 2 .  
   
   
       18 . The memory device of  claim 16  wherein the floating gate layer is either an atomic layer deposition metal or an evaporated metal.  
   
   
       19 . The memory device of  claim 13  wherein the high-k dielectric has a dielectric constant greater than silicon dioxide.  
   
   
       20 . The memory device of  claim 13  wherein the control gate is a polysilicon.