System for testing integrated circuit devices

Abstract

A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC 2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

1 . A device, comprising: 
 means for producing a plurality of test voltages, each of the plurality of test voltages having a different magnitude; and    means for sending a plurality of test signals to the means for producing to produce the plurality of test voltages.    
   
   
       2 . The device of  claim 1 , wherein: 
 the means for producing a plurality of test voltages includes means for producing a voltage of a predetermined magnitude in the integrated circuit device; and    the means for sending a plurality of test signals includes: 
 means for generating a plurality of test signals within the integrated circuit device in response to an externally generated signal, each of the test signals representing a different incremental adjustment in the magnitude of the voltage; and  
 means for applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels.  
   
   
   
       3 . A method, comprising: 
 producing a voltage of a predetermined magnitude in the integrated circuit device;    generating a plurality of test signals within the integrated circuit device in response to an externally generated signal, each of the test signals representing a different incremental adjustment in the magnitude of the voltage; and    applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels.    
   
   
       4 . The method of  claim 3 , wherein generating a plurality of test signals includes generating coded signals external to the integrated circuit device, and transmitting the coded signals into the integrated circuit device to generate the plurality of test signals within the integrated circuit device.  
   
   
       5 . The method of  claim 3 , further comprising performing a test of the integrated circuit at each of the plurality of levels.  
   
   
       6 . The method of  claim 3 , wherein the predetermined magnitude includes a setpoint value, and the plurality of levels includes at least a first increased level from the setpoint value and at least a first decreased level from the setpoint level.  
   
   
       7 . The method of  claim 3 , wherein the predetermined magnitude includes a setpoint value, and the plurality of levels includes at least a first and a second increased level from the setpoint value and at least a first and a second decreased level from the setpoint level.  
   
   
       8 . The method of  claim 3 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a substrate bias voltage (Vbb) in the integrated circuit.  
   
   
       9 . The method of  claim 3 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a boosted wordline voltage (Vccp) in the integrated circuit.  
   
   
       10 . The method of  claim 3 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a cell plate voltage in the integrated circuit.  
   
   
       11 . The method of  claim 3 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a digitline bias voltage (DVC 2 ) in the integrated circuit.  
   
   
       12 . The method of  claim 3 , wherein applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels includes programming a logic device to maintain the voltage at a predetermined adjusted level.  
   
   
       13 . A method, comprising: 
 producing a voltage of a predetermined magnitude in the integrated circuit device;    generating a plurality of test signals within the integrated circuit device in response to an externally generated signal, each of the test signals representing a different incremental adjustment in the magnitude of the voltage; and    applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels, including selectively bypassing resistances of a voltage divider network to incrementally adjust the magnitude of the voltage.    
   
   
       14 . The method of  claim 13 , further comprising conducting a static refresh test of memory cells at a predetermined one of the plurality of levels and conducting margin testing at a predetermined one of the plurality of levels.  
   
   
       15 . The method of  claim 13 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a substrate bias voltage (Vbb) in the integrated circuit.  
   
   
       16 . The method of  claim 13 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a boosted wordline voltage (Vccp) in the integrated circuit.  
   
   
       17 . The method of  claim 13 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a cell plate voltage in the integrated circuit.  
   
   
       18 . The method of  claim 13 , wherein producing a voltage of a predetermined magnitude in the integrated circuit device includes producing a digitline bias voltage (DVC 2 ) in the integrated circuit.  
   
   
       19 . A method, comprising: 
 producing a voltage of a predetermined magnitude in the integrated circuit device;    generating coded signals external to the integrated circuit device;    transmitting the coded signals into the integrated circuit device to generate a plurality of test signals within the integrated circuit device, each of the test signals representing a different incremental adjustment in the magnitude of the voltage;    applying the test signals generated within the integrated circuit device to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels; and    conducting a static refresh test of memory cells at at least one of the plurality of levels.    
   
   
       20 . The method of  claim 19 , wherein applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels includes programming a logic device to maintain the voltage at a predetermined adjusted level.  
   
   
       21 . The method of  claim 19 , wherein applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels includes selectively bypassing resistances of a voltage divider network to incrementally adjust the magnitude of the voltage.  
   
   
       22 . A method, comprising: 
 producing a voltage of a predetermined magnitude in the integrated circuit device;    generating coded signals external to the integrated circuit device;    transmitting the coded signals into the integrated circuit device to generate a plurality of test signals within the integrated circuit device, each of the test signals representing a different incremental adjustment in the magnitude of the voltage;    applying the test signals generated within the integrated circuit device to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels; and    conducting margin testing at at least one of the plurality of levels.    
   
   
       23 . The method of  claim 22 , wherein applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels includes programming a logic device to maintain the voltage at a predetermined adjusted level.  
   
   
       24 . The method of  claim 22 , wherein applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels includes selectively bypassing resistances of a voltage divider network to incrementally adjust the magnitude of the voltage.  
   
   
       25 . A method, comprising: 
 producing a voltage of a predetermined magnitude to maintain a setpoint voltage within an integrated circuit package that contains the integrated circuit device;    generating coded signals external to the integrated circuit package;    generating a plurality of test signals within the integrated circuit package in response to the externally generated coded signals, each of the test signals corresponding to one of the coded signals and representing a different incremental adjustment in the magnitude of the voltage; and    applying the test signals to a control circuit in the integrated circuit device to cause the control circuit to incrementally adjust the magnitude of the voltage within the integrated circuit device to a plurality of levels.    
   
   
       26 . The method of  claim 25 , further comprising transmitting the coded signals through address inputs into the integrated circuit package.  
   
   
       27 . The method of  claim 25 , further comprising conducting a static refresh test of memory cells at a predetermined one of the plurality of levels and conducting margin testing at a predetermined one of the plurality of levels.  
   
   
       28 . A method, comprising: 
 forming a voltage generating circuit to produce a plurality of test voltages, each of the plurality of test voltages having a different magnitude; and    forming a test circuit adapted to send a plurality of test signals that correspond to the plurality of test voltages to the voltage generating circuit to produce the plurality of test voltages.    
   
   
       29 . The method of  claim 28 , wherein forming the voltage generating circuit comprises: 
 forming a voltage producing circuit to produce a voltage; and    forming a regulating circuit coupled to the voltage producing circuit to maintain the voltage at a setpoint value.    
   
   
       30 . A method, comprising: 
 forming an integrated circuit device;    forming a voltage producing circuit located within the integrated circuit device to produce a voltage; and    forming a control circuit connected to the voltage producing circuit and located within the integrated circuit device, the control circuit being adapted to respond to an external signal to provide a selected one of a plurality of voltage increments with respect to the voltage.    
   
   
       31 . The method of  claim 30 , further comprising forming a regulatory circuit to maintain the voltage at a setpoint value.  
   
   
       32 . The method of  claim 30 , further comprising forming at least one programmable circuit coupled to the control circuit to permanently maintain the voltage at a level to which the voltage is adjusted.  
   
   
       33 . A method, comprising: 
 forming a memory device;    forming a voltage generating circuit coupled to the memory device to produce a voltage at a setpoint value;    forming a test mode enable circuit coupled to the voltage generating circuit to cause the integrated circuit device to operate in a test mode in response to coded signals generated externally of the package and applied to signal inputs of the integrated circuit device;    forming a test circuit to produce a plurality of test signals coupled to the voltage generating circuit, each of the test signals representing a different voltage magnitude; and    forming a control circuit coupled to the voltage generating circuit and responsive to the test signals to incrementally adjust the voltage relative to the setpoint value to provide a plurality of test voltages of different magnitudes for testing the memory device.    
   
   
       34 . The method of  claim 33 , wherein forming the control circuit includes forming a plurality of control devices to change the setpoint value to cause a corresponding change in the plurality of test voltages.  
   
   
       35 . A method, comprising: 
 forming a memory device; and    forming a voltage generating circuit coupled to the memory device comprising: 
 forming a voltage producing circuit to produce a bias voltage;  
 forming a regulating circuit coupled to the voltage producing circuit to maintain the bias voltage at a setpoint value and to incrementally adjust a magnitude of the voltage relative to the setpoint value to provide a plurality of voltages of different magnitudes;  
 forming a test mode enable circuit coupled to the voltage generating circuit to cause the integrated circuit device to operate in a test mode in response to a test signal generated externally of the package and applied to a signal input of the integrated circuit;  
 forming a test circuit to produce a plurality of test signals coupled to the voltage generating circuit, wherein each of the test signals represents a different adjustment value and wherein each test signal is produced in response to an external coded signal; and  
 forming a control circuit coupled to the voltage generating circuit and adapted to respond to the test signals to control the regulating circuit as a function of the test signals to incrementally adjust a magnitude of the bias voltage produced by the voltage producing circuit to provide a plurality of voltages of different magnitudes.  
   
   
   
       36 . The method of  claim 35 , wherein forming the control circuit includes forming a plurality of control devices to change the setpoint value to cause a corresponding change in the plurality of test voltages.  
   
   
       37 . A method, comprising: 
 forming an integrated circuit device;    forming a voltage producing circuit located within the integrated circuit device to produce a voltage and a plurality of voltage increments with respect to the voltage; and    forming a control circuit coupled to the voltage producing circuit and located within the integrated circuit device to incrementally adjust the voltage with a selected one of the plurality of voltage increments according to an external signal allowing the control circuit to be controlled externally of the integrated circuit device.    
   
   
       38 . The method of  claim 37 , further comprising forming a fixed reference circuit to establish the setpoint value, wherein forming the control circuit includes forming at least one circuit device adapted to respond to an externally generated signal applied to the integrated circuit device to override the fixed reference circuit and adjust the voltage relative to the setpoint value.  
   
   
       39 . A method, comprising: 
 forming a voltage generating circuit to produce a voltage at a setpoint value;    forming a test mode enable circuit coupled to the voltage generating circuit to cause the integrated circuit device to enter a test mode on receiving a test signal; and    forming a test control circuit coupled to the voltage generating circuit to cause the voltage generating circuit to perform a plurality of incremental adjustments to the voltage relative to the setpoint value.    
   
   
       40 . The method of  claim 39 , wherein forming a voltage generating circuit to produce a voltage at a setpoint value includes forming a voltage generating circuit to produce a bias voltage.  
   
   
       41 . The method of  claim 40 , wherein forming a test control circuit includes forming a test control circuit coupled to the voltage generating circuit to cause the voltage generating circuit to provide a plurality of discrete shifts in the level of the bias voltage.  
   
   
       42 . A method, comprising: 
 forming a voltage generating circuit to produce a voltage at a setpoint value;    forming a test control circuit coupled to the voltage generating circuit to cause the voltage generating circuit to perform a plurality of incremental adjustments to the voltage relative to the setpoint value; and    forming a programmable circuit coupled to the voltage generating circuit to modify the setpoint value corresponding to a modify signal.    
   
   
       43 . The method of  claim 42 , further comprising packaging the voltage generating circuit, the test control circuit, the programmable circuit and the integrated circuit device in a package.  
   
   
       44 . The method of  claim 42 , further comprising forming a test mode enable circuit coupled to the voltage generating circuit to cause the integrated circuit device to enter a test mode on receiving a test signal.  
   
   
       45 . A method, comprising: 
 forming a voltage producing circuit with an oscillator circuit and a charge pump circuit responsive to the oscillator circuit to produce a bias voltage for an integrated circuit device;    forming a regulating circuit coupled to the voltage producing circuit to maintain a magnitude of the bias voltage at a setpoint value, including forming a fixed reference circuit with a plurality of level setting devices to establish the setpoint value for the voltage; and    forming a control circuit coupled to the regulating circuit to adjust the magnitude of the voltage to at least first and second different values relative to the setpoint value, including forming a plurality of control devices to control the fixed reference circuit to change the setpoint value to cause a corresponding change in the magnitude of the voltage produced by the voltage producing circuit.    
   
   
       46 . The method of  claim 45 , wherein forming the plurality of control devices includes forming a device to provide a bypass path around at least one of the level setting devices of the fixed reference circuit.  
   
   
       47 . The method of  claim 45 , wherein forming the control circuit includes forming a variable reference circuit with a plurality of level setting devices and at least one pass transistor to couple the variable reference circuit to a setpoint node of the regulating circuit to provide incremental adjustment in the voltage.