Production method of wiring substrate having ultra-fine pattern, and wiring substrate

Abstract

To produce a wiring substrate by employing a semi-additive method, the invention provides a production method of a wiring substrate, and a wiring substrate, that suppress the formation of undercut of an electrolytic copper plating layer during base etching and capable of ultra-fine wiring of a line/space size of 25/25 μm or below and further 10/10 μm or below. When producing a wiring substrate, the method of the invention includes the steps of applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer; applying a resist pattern exposing a portion for forming a wiring pattern on the surface of the electroless copper plating layer; plating metals different from copper or alloys containing at least one kind of the metals to the exposed portion to form an etching barrier plating layer; plating an etching barrier metal to form an etching barrier metal plating layer; applying electrolytic copper plating to the surface of the etching barrier metal plating layer to form wiring having a conductor layer including an electroless copper plating layer, the etching barrier metal plating layer and the electrolytic copper plating layer and the electrolytic copper plating layer; removing the resist pattern; and etching and removing the electroless copper plating layer exposed on the surface to form a wiring pattern.

1 . A production method of a wiring substrate comprising the steps of: 
 applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer;    applying a resist pattern exposing a portion for forming a wiring pattern on the surface of said electroless copper plating layer;    plating metals different from copper or alloys containing at least one kind of said metals to said exposed portion to form an etching barrier plating layer;    applying electrolytic copper plating to the surface of said etching barrier plating layer to form an electrolytic copper plating layer;    removing said resist pattern; and    etching and removing said electroless copper plating layer exposed on the surface to form a wiring pattern.    
   
   
       2 . A production method of a wiring substrate according to  claim 1 , wherein said etching barrier plating layer is formed of a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of said metals.  
   
   
       3 . A production method of a wiring substrate comprising the steps of: 
 applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer;    applying a resist pattern exposing a portion for forming a wiring pattern on the surface of said electroless copper plating layer;    plating metals different from copper or alloys containing at least one kind of said metals to said exposed portion to form an etching barrier plating layer;    alloying said metals or said alloys of said etching barrier plating layer and copper of said electroless copper plating layer to form an alloy layer;    applying electrolytic copper plating to the surface of said alloy layer to form an electrolytic copper plating layer;    removing said resist pattern; and    etching and removing said electroless copper plating layer exposed on the surface to form a wiring pattern.    
   
   
       4 . A production method of a wiring substrate according to  claim 3 , wherein said etching barrier plating layer is formed of a member selected from the group consisting of Sn, Zn and In and alloys containing at least one kind of said metals.  
   
   
       5 . A production method of a wiring substrate comprising the steps of: 
 applying electroless copper plating to a surface of a substrate made of a resin having an electric insulating property to form an electroless copper plating layer;    applying a resist pattern exposing a portion for forming a wiring pattern on the surface of said electroless copper plating layer;    conducting substitution plating for replacing copper of said electroless copper plating layer of said exposed portion by using metals different from copper of said electroless copper plating layer or alloys containing at least one kind of said metals to form an etching barrier substitution plating layer;    applying electrolytic copper plating to the surface of said etching barrier substitution plating layer to form an electrolytic copper plating layer;    removing said resist pattern;    etching and removing said electroless copper plating layer exposed on the surface; and    forming said wiring pattern.    
   
   
       6 . A production method of a wiring substrate according to  claim 5 , wherein said etching barrier substitution plating layer is formed of a member selected from the group consisting of Sn, Ni, Co, Zn and Ag and alloys containing at least one kind of said metals.  
   
   
       7 . A wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an electroless copper plating layer, an etching barrier plating layer formed by metals different from copper or alloys containing at least one kind of said metals on said electroless copper plating layer, and an electrolytic copper plating layer formed on said etching barrier plating layer.  
   
   
       8 . A wiring substrate according to  claim 7 , wherein said etching barrier metal plating layer is formed of a member selected from the group consisting of Ni, Sn, Co, Zn, In and Ag and alloys containing at least one kind of said metals.  
   
   
       9 . A wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an alloy layer of an alloy between copper and metals different from copper or alloys containing at least one kind of said metals, and an electrolytic copper plating layer formed on said alloy layer.  
   
   
       10 . A wiring substrate according to  claim 9 , wherein said alloy layer is formed of an alloy of copper and a member selected from the group consisting of Ni, Sn, Co, Zn and In and alloys containing at least one kind of said metals.  
   
   
       11 . A semiconductor wiring substrate having wiring formed into a pattern on a substrate made of a resin having an electric insulating property, wherein said wiring includes an etching barrier substitution plating layer formed of metals different from copper or alloys containing at least one kind of said metals, and an electrolytic copper plating layer formed on said etching barrier substitution layer.  
   
   
       12 . A wiring substrate according to  claim 11 , wherein said etching barrier substitution plating layer is formed of a member selected from the group consisting of Sn, Ni, Co, Zn, and Ag and alloys containing at least one kind of said metals.