Pipelined clock stretching circuitry and method for I2C logic system

Abstract

A system for increasing the data throughput of an I 2 C bus including a serial clock conductor ( 3 ) for conducting a serial clock signal (SCK) and a serial data conductor ( 2 ) for conducting a serial data signal (SDA) includes clock-stretching control circuitry ( 15 ) coupled to the serial clock conductor ( 3 ) for stretching the serial clock signal (SCK) by holding the serial clock conductor ( 3 ) at a predetermined level to cause a master device ( 10 ) to stop sending the serial clock signal, and circuitry (FIG. 3 ) in the slave device ( 5 ) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device ( 5 ) that stretching of the serial clock signal (SCK) is unnecessary.

1 . A system for increasing the data throughput of an I 2 C bus including a serial clock conductor for conducting a serial clock signal and a serial data conductor for conducting a serial data signal, the system comprising: 
 (a) a master device coupled to the serial clock conductor and the serial data conductor;    (b) a slave device coupled to the serial clock conductor and the serial data conductor, the slave device including clock stretch control circuitry coupled to the serial clock conductor for stretching the serial clock signal by holding the serial clock conductor at a predetermined level to cause the master device to stop sending the serial clock signal; and    (c) circuitry in the slave device for releasing the stretching of the serial clock signal in response to a determination by the slave device that no stretching of the serial clock signal is required.    
   
   
       2 . A system for controlling clock stretching in an I 2 C system including a serial clock conductor conducting a serial clock signal and a serial data conductor conducting a serial data signal, comprising: 
 (a) a slave device including 
 i. a switch coupled between the serial clock conductor and a reference voltage conductor,  
 ii. a stretch release control circuit coupled to a slave CPU and a control circuit and also coupled to a control electrode of the switch for storing stretch release information produced by the slave CPU during reception of a byte of information by the slave device, stretching the serial clock signal by closing the switch, and discontinuing the stretching by opening the switch, and  
 iii. the slave CPU being coupled to the stretch release control circuit and operative, in response to a determination by the slave CPU that no stretching of the serial clock signal is required, to set the stretch release information to a value that causes the stretch release control circuit to hold the switch open after the byte of information is received; and  
   (b) a master device coupled to the serial clock conductor and the serial data conductor for sending the byte of information on the serial data conductor, for responding to stretching of the serial clock signal to discontinue clock signal transmission and data transmission, and for responding to release of the serial clock conductor by continuing clock signal transmission and data transmission.    
   
   
       3 . The system of  claim 2  wherein the control circuit is coupled between the serial data conductor and the slave CPU to control operation of the slave CPU in response to information received from the serial data conductor.  
   
   
       4 . The system of  claim 2  wherein the slave CPU makes the determination that a predetermined stretching of the serial clock signal needs to be released after reception of the byte of information is complete.  
   
   
       5 . The system of  claim 2  wherein the determination that the serial clock conductor needs to be released after reception of the byte of information is complete is made in advance by means of a program executed by the slave CPU.  
   
   
       6 . The system of  claim 2  wherein the switch includes an MOS transistor coupled between the serial clock conductor and the reference voltage conductor, a gate of the MOS transistor being coupled to the stretch release control circuit.  
   
   
       7 . The system of  claim 3  including a shift register and a buffer circuit coupling the serial clock conductor to the control circuit.  
   
   
       8 . The system of  claim 2  wherein the stretch release control circuit includes a first circuit responsive to a start stretch signal produced by the control circuit to produce an internal stretch signal for causing closing of the switch, and also includes a second circuit for producing a stretch release signal in response to the stored stretch release information produced by the slave CPU, and also includes a third circuit which functions to cause opening of the switch in response to the signal and the stretch release signal.  
   
   
       9 . The system of  claim 8  wherein the third circuit performs a logical ANDing operation on the stretch signal and the stretch release signal to cause release of the serial clock conductor in response to the internal stretch signal.  
   
   
       10 . A method for controlling clock stretching in an I 2 C system including a serial clock conductor conducting a serial clock signal and a serial data conductor conducting a serial data signal, the method comprising: 
 (a) providing a slave device including a slave CPU coupled to a stretch release control circuit coupled to a control electrode of a switch coupled between the serial clock conductor and a reference voltage conductor;    (b) determining by means of the slave CPU whether a stretching of the serial clock signal needs to be suppressed after reception of the byte of information is complete and storing stretch release information indicative of whether the stretching of the serial clock signal needs to be suppressed; and    (c) suppressing the stretching by opening the switch in response to the stored stretch release information after the byte of information is received if the stored stretch release information indicates that the stretching of the serial clock signal needs to be suppressed.    
   
   
       11 . The method of  claim 10  including allowing the stretching of the serial clock signal to occur if the stored stretch release information does not indicate that the stretching of the serial clock signal needs to be suppressed.  
   
   
       12 . The method of  claim 10  including providing a master device coupled to the serial clock conductor and the serial data conductor for sending the byte of information on the serial data conductor, responding to stretching of the serial clock signal to discontinue clock signal transmission and data transmission, and responding to the discontinuing of the stretching by continuing transmission of the serial clock signal and the serial data signal.  
   
   
       13 . The method of  claim 10  including operating a control circuit coupled between the serial data conductor and the slave CPU to control operation of the slave CPU in response to information received from the serial data conductor.  
   
   
       14 . The method of  claim 10  including operating the slave CPU to make a determination whether the serial clock conductor needs to be released after reception of the byte of information is complete.  
   
   
       15 . The method of  claim 10  including operating the slave to execute a program which determines in advance whether a stretching of the serial clock signal needs to be released after reception of the byte of information is complete.  
   
   
       16 . The method of  claim 12  including coupling the control circuit to the serial clock conductor by means of a shift register and a buffer circuit.  
   
   
       17 . The method of  claim 10  including operating the slave CPU to write a start stretch signal into a stretch control bit in response to a value of the stretch release information that causes the stretch release circuit to open the switch, and then producing a stretch signal, closing the switch, producing a stretch release signal in response to the start stretch signal, and opening the switch in response to the stretch release signal.  
   
   
       18 . The method of  claim 17  including performing a logical ANDing operation on the stretch signal and the stretch release signal to cause release of a stretching of the serial clock signal caused by the stretch signal.  
   
   
       19 . A system for controlling clock stretching in an I 2 C system including a serial clock conductor conducting a serial clock signal and a serial data conductor conducting a serial data signal, the system comprising: 
 (a) a slave device including a slave CPU coupled to a stretch release control circuit coupled to a control electrode of a switch coupled between the serial clock conductor and a reference voltage conductor;    (b) means for determining whether a stretching of the serial clock signal needs to be suppressed after reception of the byte of information is complete and storing stretch release information indicative of whether the stretching of the serial clock signal needs to be suppressed; and    (c) means for suppressing the stretching by opening the switch in response to the stored stretch release information after the byte of information is received if the stored stretch release information indicates that the stretching of the serial clock signal needs to be suppressed.    
   
   
       20 . The system of  claim 19  including means for allowing the stretching of the serial clock signal to occur if the stored stretch release information does not indicate that the stretching of the serial clock signal needs to be suppressed.