System and method for using a plurality of heterogeneous processors in a common computer system

Abstract

A system for using a plurality of heterogeneous processors in a common computer system is presented. Each processor type in the heterogeneous group handles a particular instruction set. The processors share a common memory using a common bus. In one embodiment, one of the processor types accesses the memory using DMA instructions. In another embodiment, a cache for each type of processor is stored in the common memory pool. In one embodiment, one or more PowerPC processors shares a memory with one or more Synergistic Processing Complex (SPC). A common table is used to track and maintain memory for the various processors.

1 . A plurality of heterogeneous processors, comprising: 
 one or more first processors that are adapted to process a first instruction set;    one or more second processors that are adapted to process a second instruction set; and    wherein the first processors and the second processors share a memory.    
   
   
       2 . The plurality of heterogeneous processors as described in  claim 1  wherein at least one of the first processors is a PowerPC and wherein at least one of the second processor is a synergistic processing complex.  
   
   
       3 . The plurality of heterogeneous processors as described in  claim 2  wherein each synergistic processing complex further includes: 
 a synergistic processing unit;    a local storage; and    a memory management unit, the memory management unit including a direct memory access controller.    
   
   
       4 . The plurality of heterogeneous processors as described in  claim 3  wherein the local storage is shared with at least one of the first processors.  
   
   
       5 . The plurality of heterogeneous processors as described in  claim 1  further comprising: 
 an operating system that runs on one of the first processors, the first processor controlling a memory map that corresponds to the shared memory.    
   
   
       6 . The plurality of heterogeneous processors as described in  claim 1  wherein the shared memory, the first processors, and the second processors are located on a single substrate.  
   
   
       7 . The plurality of heterogeneous processors as described in  claim 1  further comprising: 
 a common bus that interconnects the shared memory, the first processors, and the second processors.    
   
   
       8 . The plurality of heterogeneous processors as described in  claim 7  wherein the common bus is an on-chip coherent multi-processor bus.  
   
   
       9 . The plurality of heterogeneous processors as described in  claim 1  further comprising: 
 a plurality of interface controllers;    a plurality of interface pins;    flexible input-output logic that is adapted to assign one or more interface pins from the plurality of interface pins to one of the plurality of interface controllers.    
   
   
       10 . The plurality of heterogeneous processors as described in  claim 9  wherein the assigning is managed by one of the first processors.  
   
   
       11 . The plurality of heterogeneous processors as described in  claim 9  wherein the assigning is performed at system initialization.  
   
   
       12 . The plurality of heterogeneous processors as described in  claim 9  wherein the assigning is performed at system build.  
   
   
       13 . The plurality of heterogeneous processors as described in  claim 1  wherein each of the plurality of second processors is adapted to process a different instruction set.  
   
   
       14 . The plurality of heterogeneous processors as described in  claim 13  wherein one of the second processors is adapted to pass data to a different second processor using an on-chip coherent multi-processor bus.  
   
   
       15 . The plurality of heterogeneous processors as described in  claim 1  wherein the memory includes a plurality of regions and wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region.  
   
   
       16 . The plurality of heterogeneous processors as described in  claim 1  wherein at least one of the second processors from the plurality of second processors uses private memory.  
   
   
       17 . A method for handling a plurality of heterogeneous processors that share a common memory, said method comprising: 
 identifying a memory size requirement that corresponds to a first processor, the first processor adapted to process a first instruction set;    configuring the common memory in response to the identification;    determining whether there is unassigned memory located on the common memory after the configuration; and    assigning the unassigned memory to a second processor, the second processor adapted to process a second instruction set.    
   
   
       18 . The method as described in  claim 17  wherein the first processor is a Power PC and wherein the second processor is a synergistic processing unit.  
   
   
       19 . The method as described in  claim 17  further comprising: 
 managing the common memory using a common memory map.    
   
   
       20 . The method as described in  claim 19  wherein one of the first processors includes an operating system whereby the first processor controls the common memory map.  
   
   
       21 . The method as described in  claim 19  wherein the common memory map includes a plurality of regions, wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region.  
   
   
       22 . The method as described in  claim 17  wherein at least one of the second processors uses a direct memory access controller for accessing the common memory.  
   
   
       23 . A computer program product stored on a computer operable media for handling a plurality of heterogeneous processors that share a common memory, said computer program product comprising: 
 means for identifying a memory size requirement that corresponds to a first processor, the first processor adapted to process a first instruction set;    means for configuring the common memory in response to the identification;    means for determining whether there is unassigned memory located on the common memory after the configuration; and    means for assigning the unassigned memory to a second processor, the second processor adapted to process a second instruction set.    
   
   
       24 . The computer program product as described in  claim 23  wherein the first processor is a Power PC and wherein the second processor is a synergistic processing unit.  
   
   
       25 . The computer program product as described in  claim 23  further comprising: 
 means for managing the common memory using a common memory map.    
   
   
       26 . The computer program product as described in  claim 25  wherein one of the first processors includes an operating system whereby the first processor controls the common memory map.  
   
   
       27 . The computer program product as described in  claim 25  wherein the common memory map includes a plurality of regions, wherein at least one of the regions is selected from the group consisting of an external system memory region, a local storage aliases region, a TLB region, an MFC region, an operating system region, and an I/O devices region.  
   
   
       28 . The computer program product as described in  claim 23  wherein at least one of the second processors uses a direct memory access controller for accessing the common memory.