Method frame storage using multiple memory circuits

Abstract

A memory architecture in accordance with an embodiment of the present invention improves the speed of method invocation. Specifically, method frames of method calls are stored in two different memory circuits. The first memory circuit stores the execution environment of each method call, and the second memory circuit stores parameters, variables or operands of the method calls. In one embodiment the execution environment includes a return program counter, a return frame, a return constant pool, a current method vector, and a current monitor address. In some embodiments, the memory circuits are stacks; therefore, the stack management unit to cache can be used to cache either or both memory circuits. The stack management unit can include a stack cache to accelerate data transfers between a stack-based computing system and the stacks. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. When the stack-based computing system is popping data off of the stack and a fill condition occurs, the fill control unit transfer data from the stack to the bottom of the stack cache to maintain the top portion of the stack in the stack cache. Typically, a fill condition occurs as the stack cache becomes empty and a spill condition occurs as the stack cache becomes full.

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         57 . A method of generating executable code for a computer program in source code form, said method comprising: 
 determining whether said executable code is for execution by a microprocessor communicatively connected to a network and receiving said executable code therefrom for execution;    determining whether said executable code is for execution by a microprocessor connected to a local memory and receiving said executable code therefrom for execution; and    generating a first executable code with code verification in the event said first executable code is to be received from said network for execution by said microprocessor; or    generating a second executable code without code verification in the event said second executable code is to be received from said local memory for execution by said microprocessor.