Methods and apparatus for forming barrier layers in high aspect ratio vias

Abstract

In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

1 - 57 . (canceled)  
   
   
       58 . A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising: 
 (a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;    (b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the wafer substrate;    (c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and    (d) depositing the metal conductive layer over the surface of the wafer substrate.    
   
   
       59 . The method of  claim 58 , wherein (b) and (c) are performed in the same processing chamber.  
   
   
       60 . The method of  claim 59 , wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.  
   
   
       61 . The method of  claim 58 , further comprising a degas operation prior to (a).  
   
   
       62 . The method of  claim 58 , wherein (a) comprises depositing the first portion of diffusion barrier to a thickness of between about 5 and 100 angstroms over field regions on the surface of the wafer substrate.  
   
   
       63 . The method of  claim 58 , wherein (b) comprises depositing the second portion of diffusion barrier elsewhere on the wafer to between about 10 and 50 Å at least as on sidewalls of the plurality of vias.  
   
   
       64 . The method of  claim 63 , wherein (b) further comprises depositing the second portion of diffusion barrier elsewhere on the wafer to between about 200 and 1000 Å on field regions of the wafer substrate and a plurality of horizontal trench surfaces of the wafer substrate.  
   
   
       65 . The method of  claim 58 , wherein (c) comprises depositing the third portion of diffusion barrier to between about 20 and 40 Å on bottoms of the plurality of vias.  
   
   
       66 . The method of  claim 58 , wherein (a) comprises sputtering a metal from a target having an applied DC power of between about 10 and 50 kilowatts, without significantly biasing the wafer substrate.  
   
   
       67 . The method of  claim 58 , wherein (a) comprises using 
 chemical vapor deposition (CVD),    physical vapor deposition (PVD), or    atomic layer deposition (ALD).    
   
   
       68 . The method of  claim 58 , wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of 
 tantalum,    nitrogen-doped tantalum,    tantalum nitride,    titanium nitride,    tungsten nitride and    silicon containing versions of any of these.    
   
   
       69 . The method of  claim 58 , wherein (b) comprises sputtering a metal from a target having an applied DC power of less than about 0.5 kilo Watts, while applying a bias to the wafer substrate.  
   
   
       70 . The method of  claim 69 , wherein the bias comprises RF power of between about 400 and 1000 Watts  
   
   
       71 . The method of  claim 58 , wherein (b) is performed under conditions having an etch-to-deposition ratio of greater than 1 at the bottoms of the vias.  
   
   
       72 . The method of  claim 58 , wherein (c) comprises a process selected from the group consisting of 
 chemical vapor deposition (CVD),    physical vapor deposition (PVD), and    atomic layer deposition (ALD).    
   
   
       73 . The method of  claim 58 , further comprising, after (c) but prior to (d), etching through some of the third portion of the diffusion barrier at the bottoms of a plurality of vias, without etching to expose an underlying metal structure.  
   
   
       74 . The method of  claim 58 , wherein (d) comprises depositing copper containing metal over the surface of the wafer substrate.  
   
   
       75 . The method of  claim 74 , wherein the metal is a copper seed layer.  
   
   
       76 . The method of  claim 58 , wherein at least (b) and (c) are performed in the same processing chamber.  
   
   
       77 . The method of  claim 58 , wherein at least (a) through (c) are all performed in the same processing chamber.  
   
   
       78 . A method for depositing a diffusion barrier and a metal conductive layer on a partially fabricated integrated circuit containing a plurality of unlanded vias, the method comprising: 
 (a) depositing a first portion of the diffusion barrier on the surface of the partially fabricated integrated circuit;    (b) etching through at least part of the first portion of the diffusion barrier at the bottoms of a plurality of unlanded and landed vias to expose at least part of an underlying metal layer while simultaneously depositing a second portion of the diffusion barrier on at least field regions of the surface of the partially fabricated integrated circuit;    (c) depositing a third portion of the diffusion barrier, which covers at least the bottoms of the vias; and    (d) depositing the metal conductive layer over the surface of the wafer substrate.    
   
   
       79 . The method of  claim 78 , wherein (b) and (c) are performed in the same processing chamber.  
   
   
       80 . The method of  claim 79 , wherein the processing chamber is a plasma physical vapor deposition (PVD) chamber.  
   
   
       81 . The method of  claim 78 , wherein (a) and/or (c) comprise a processes selected from the group consisting of 
 chemical vapor deposition (CVD),    physical vapor depositon (PVD), and    atomic layer deposition (ALD).    
   
   
       82 . The method of  claim 78 , wherein at least one portion of the diffusion barrier comprises a material selected from the group consisting of 
 tantalum,    nitrogen-doped tantalum,    tantalum nitride,    titanium nitride,    tungsten nitride and    silicon containing versions of any of these.    
   
   
       83 . The method of  claim 78 , wherein (b) comprises sputtering a metal from a target having an applied DC power of less than about 0.5 kilo Watts, while applying a bias to the wafer substrate.  
   
   
       84 . The method of  claim 78 , wherein (d) comprises depositing copper-containing metal over the surface partially fabricated integrated circuit.  
   
   
       85 . The method of  claim 84 , wherein the metal is a copper seed layer.  
   
   
       86 . The method of  claim 78 , wherein at least (a) and (b) are performed in the same processing chamber.  
   
   
       87 . The method of  claim 78 , wherein at least (b) and (c) are performed in the same processing chamber.  
   
   
       88 . The method of  claim 78 , wherein at least (a) through (c) are all performed in the same processing chamber.