Apparatus and method for generating clock signals

Abstract

A delay-locked loop circuit generates a first clock signal. The delay-locked loop circuit includes a first delay element coupled in a feedback path of the delay-locked loop circuit to advance the first clock signal relative to a reference clock signal by a first time period. A second delay element is coupled to receive the first clock signal from the delay-locked loop circuit. The second delay element also outputs a second clock signal that is delayed relative to the first clock signal by the first time period. The delay-locked loop circuit may include a phase detector to identify phase differences between the first clock signal and the reference clock signal. A third delay element may be coupled between the delay-locked loop circuit and the second delay element.

1 . A system, comprising: 
 a random access memory device;    a first signal line coupled to the random access memory device, the first signal line to carry a first signal;    a second signal line coupled to the random access memory device, the second signal line to carry a second signal; and    a memory controller coupled to the first signal line and the second signal line, wherein the memory controller includes a delay locked loop to generate the first signal, wherein, the first signal is used to transmit data to the random access memory device, the delay locked loop to receive the second signal such that the second signal is used to sample read data provided by the memory device.