Memory controller which increases bus bandwidth, data transmission method using the same, and computer system having the same

Abstract

A memory controller increases the effective bus bandwidth of a computer system. The memory controller includes a first port and a second port which receive and transmit N-bit data values, respectively; a third port receiving and transmitting 2N-bit data values; and a fourth port and a fifth port receiving and transmitting the N-bit data values, respectively. Here, two N-bit data values are simultaneously fetched from a memory device corresponding to the first port via the first port and a memory device corresponding to the second port in response to a command signal and an address input via the third port, the two fetched N-bit data values are combined into a 2N-bit data value, and the 2N-bit data value is transmitted to the third port. In addition, an N-bit data value is fetched from a corresponding memory device via the first port and/or second port in response to a command signal and address input via the fourth port and/or fifth port, and the fetched N-bit data value is transmitted to the fourth port and/or fifth port.

1 . A memory controller comprising: 
 multiple N-bit wide memory ports, each communicating with a respective N-bit memory device;    at least one 2N-bit wide port communicating with at least one 2N-bit wide device;    wherein data received from the respective N-bit memory devices at least two of the multiple N-bit wide memory ports are combined and transmitted to the 2N-bit wide device through the at least one 2N-bit wide port;    wherein data received from the at least one 2N-bit device through the at least one 2N-bit wide port are divided into two N-bit data and transmitted to at least two of the multiple N-bit memory devices through the respective at least two N-bit wide memory ports.    
   
   
       2 . The memory controller of  claim 1 , wherein the at least one 2N-bit wide device is a central processing unit (CPU).  
   
   
       3 . The memory controller of  claim 1 , wherein the memory controller further comprises multiple N-bit wide peripheral ports communicating with multiple N-bit wide peripheral devices.  
   
   
       4 . The memory controller of  claim 3 , wherein data received at the multiple N-bit wide memory ports is transmitted to the multiple N-bit wide peripheral devices through the multiple N-bit wide peripheral ports.  
   
   
       5 . The memory controller of  claim 3 , wherein the multiple N-bit peripheral devices are each at least one of peripheral component interconnect (PCI) device, an Ethernet device, and a universal asynchronous receiver/transceiver (UART) device.  
   
   
       6 . The memory controller of  claim 4 , wherein the data from the N-bit wide memory ports is received from the corresponding multiple memory devices in response to a command and an address signal input received through the corresponding multiple N-bit wide peripheral ports.  
   
   
       7 . The memory controller of  claim 6 , wherein the command signal comprises a signal for fetching data.  
   
   
       8 . The memory controller of  claim 3 , wherein the multiple N-bit wide peripheral ports are connected to the corresponding multiple N-bit wide peripheral devices via N-bit buses.  
   
   
       9 . The memory controller of  claim 1 , wherein the data from at least two of the multiple N-bit wide memory ports is received from at least two of the multiple memory devices in response to a command and an address signal input received through the at least one 2N-bit port.  
   
   
       10 . The memory controller of  claim 9 , wherein the command signal comprises a signal for fetching data.  
   
   
       11 . The memory controller of  claim 1 , wherein the multiple N-bit wide memory ports are connected to the corresponding multiple N-bit memory devices via independent N-bit buses.  
   
   
       12 . The memory controller of  claim 1 , wherein the at least one 2N-bit wide port is connected to the 2N-bit wide device via a 2N-bit bus.  
   
   
       13 . The memory controller of  claim 1 , wherein N is 32.  
   
   
       14 . A computer system comprising: 
 multiple memory devices that store data and instructions;    at least one 2N-bit device that controls and manages the computer system;    multiple N-bit peripheral devices that exchange data with the multiple memory devices;    a memory controller that controls the exchange of data among the multiple memory devices and the at least one 2N-bit device, and among the multiple memory devices and the multiple N-bit peripheral devices;    wherein the memory controller comprises:    multiple N-bit wide memory ports that communicate N-bit data with the corresponding multiple memory devices via corresponding multiple N-bit buses;    at least one 2N-bit wide port that communicates 2N-bit data with the 2N-bit device via a corresponding at least one 2N-bit bus;    multiple N-bit wide peripheral ports, each communicating N-bit data with the corresponding multiple N-bit peripheral devices via corresponding N-bit buses;    wherein the data received from respective memory devices at least two of the multiple N-bit wide memory ports are combined and transmitted to the 2N-bit wide device through the at least one 2N-bit wide port;    wherein data received from the at least one 2N-bit device through the at least one 2N-bit wide port, are divided into two N-bit data and transmitted to at least two of the multiple memory devices, through the respective at least two N-bit wide ports.    
   
   
       15 . The computer system of  claim 14 , wherein the at least one 2N-bit wide device is a central processing unit (CPU).  
   
   
       16 . The computer system of  claim 14 , wherein the multiple N-bit peripheral devices are each at least one of peripheral component interconnect (PCI) device, an Ethernet device, and a universal asynchronous receiver/transceiver (UART) device.  
   
   
       17 . The computer system of  claim 16 , wherein data received at the multiple N-bit wide memory ports is transmitted to the multiple N-bit wide peripheral devices through the multiple N-bit wide peripheral ports.  
   
   
       18 . The memory controller of  claim 17 , wherein the data from the N-bit wide memory ports is received from the corresponding multiple memory devices in response to a command and an address signal input received through the corresponding multiple N-bit wide peripheral ports.  
   
   
       19 . The memory controller of  claim 14 , wherein the data from at least two of the multiple N-bit wide memory ports is received from at least two of the multiple memory devices in response to a command and an address signal input received through the at least one 2N-bit port.  
   
   
       20 . The memory controller of  claim 19 , wherein the command signal comprises a signal for fetching data.  
   
   
       21 . The memory controller of  claim 14 , wherein N is 32.  
   
   
       22 . A data transmission method performed by a memory controller including multiple N-bit wide memory ports that communicate N-bit data values, at least one 2N-bit wide port that communicates 2N-bit data values, and multiple N-bit wide peripheral ports that communicate N-bit data values, the method comprising: 
 receiving at least one of a command and address input via the at least one 2N-bit wide port, and a command signal and address signal input via at least one of the multiple N-bit wide peripheral ports; and    fetching N-bit data values simultaneously from corresponding memory devices via the multiple N-bit wide memory ports in response to the command signal and address signal input via the at least one 2N-bit wide port, combining them to form a fetched 2N-bit data value and transmitting the fetched 2N-bit data value to the at least one 2N-bit device.    receiving 2N-bit data values input via the at least one 2N-bit wide port, dividing the 2N-bit data values into two N-bit data values, and outputting the two N-bit data values to the corresponding multiple memory devices via the multiple corresponding N-bit wide memory ports.    
   
   
       23 . The method of  claim 22 , wherein the method further includes fetching the N-bit data values from at least one of the multiple memory devices via at least one of the corresponding multiple N-bit wide memory ports in response to the command signal and address input via the at least one of the multiple N-bit wide peripheral ports, and transmitting the fetched N-bit data value to at least one of the multiple N-bit wide peripheral ports.  
   
   
       24 . The method of  claim 22 , wherein the N-bit data value input via the at least one of the multiple N-bit wide peripheral ports is output to the corresponding memory device via the at least one of the multiple corresponding N-bit wide ports.  
   
   
       25 . A data transmission method performed by a memory controller including multiple N-bit wide memory ports that communicate N-bit data values, at least one 2N-bit wide port that communicates 2N-bit data values, and multiple N-bit wide peripheral ports that communicate N-bit data values, the method comprising: 
 receiving at least one of a command and address input via the at least one 2N-bit wide port, and a command signal and address signal input via at least one of the multiple N-bit wide peripheral ports; and    receiving 2N-bit data values input via the at least one 2N-bit wide port and dividing the 2N-bit data values into two N-bit data values and outputting the two N-bit data values to corresponding multiple memory devices via the multiple corresponding N-bit wide memory ports    fetching the N-bit data values from at least one of the multiple memory devices via at least one of the corresponding multiple N-bit wide memory ports in response to the command signal and address input via the at least one of the multiple N-bit wide peripheral ports, and transmitting the fetched N-bit data value to at least one of the multiple N-bit wide peripheral ports.    
   
   
       26 . The method of  claim 25 , wherein the method further includes fetching N-bit data values simultaneously from corresponding memory devices via the multiple N-bit wide memory ports in response to the command signal and address signal input via the at least one 2N-bit wide port, combining them to form a fetched 2N-bit data value and transmitting the fetched 2N-bit data value to the at least one 2N-bit device.  
   
   
       27 . The method of  claim 25 , wherein the N-bit data value input via the at least one of the multiple N-bit peripheral devices is output to the corresponding memory device via the at least one of the multiple corresponding N-bit wide memory ports.