Adjustable timing circuit of an integrated circuit

Abstract

An adjustable timing circuit includes non-volatile programmable fuses and adjustable delay elements. A propagation time of the delay element is selected with the non-volatile fuses. The delay element can include capacitors that are selectively coupled to a propagation path in response to the data stored in the fuse circuits. In one embodiment, data stored in the programmed fuses is copied to volatile latch circuits for use during operation of the timing circuit. The adjustable timing circuit can be provided in any integrated circuit, but is particularly useful in memory devices. The timing system allows for testing and fine-tuning signal processing in the integrated circuits.

1 . A method for testing a memory device comprising a signal propagation path, the method comprising: 
 programming a plurality of non-volatile fuses to store first data;    selectively coupling one or more capacitors to the propagation path in response to the first data to provide a first propagation path delay time and an edge position for edges of signals;    testing the memory using the first propagation path delay time;    programming the plurality of non-volatile fuses to store second data;    selectively coupling one or more capacitors to the propagation path in response to the second data to provide a second propagation path delay time; and    testing the memory using the second propagation path delay time.    
   
   
       2 . The method of  claim 1  wherein the memory device is a flash memory having an array of floating gate memory cells and the plurality of non-volatile fuses comprise floating gate transistors.  
   
   
       3 . The method of  claim 1  further comprising: 
 copying the first data from the plurality of non-volatile fuses to a plurality of latches before selectively coupling one or more capacitors to the propagation path in response to the first data; and    copying the second data from the plurality of non-volatile fuses to the plurality of latches before selectively coupling one or more capacitors to the propagation path in response to the second data.    
   
   
       4 . The method of  claim 1  wherein selectively coupling comprises switching the one or more capacitors to the propagation path in response to a volatile latch circuit.  
   
   
       5 . The method of  claim 1  wherein programming comprises biasing the plurality of non-volatile fuses with a voltage greater than V CC .  
   
   
       6 . A method for testing a floating gate memory array comprising a signal propagation path having an adjustable delay, the method comprising: 
 programming a plurality of non-volatile fuses to store first data;    selectively creating a first propagation path delay time and an edge position for edges of signals in response to the first data; and    testing the memory using the first propagation path delay time and the edge positions.    
   
   
       7 . The method of  claim 6  wherein selectively creating the first propagation path comprises switching at least one capacitor to the propagation path in response to the first data.  
   
   
       8 . The method of  claim 6  wherein the first propagation path delay time is one to three units of time.  
   
   
       9 . The method of  claim 7  wherein switching at least one capacitor comprises switching one of three capacitors.  
   
   
       10 . The method of  claim 6  and further including adjusting the first propagation path delay time in response to a failed test.  
   
   
       11 . The method of  claim 10  wherein a failed test comprises a time interval between at least two memory signals being too short.  
   
   
       12 . A method for testing a flash memory device comprising a signal propagation path, the method comprising: 
 programming a plurality of non-volatile fuses to store first data;    selectively coupling one or more capacitors to the signal propagation path in response to the first data to provide a first propagation path delay time and an edge position for edges of signals; and    testing the memory using the first propagation path delay time.    
   
   
       13 . The method of  claim 12  and further including changing the first propagation path delay time by increasing the quantity of capacitors coupled to the signal propagation path.  
   
   
       14 . The method of  claim 12  and further including changing the first propagation path delay time by decreasing the quantity of capacitors coupled to the signal propagation path.  
   
   
       15 . The method of  claim 12  wherein selectively coupling comprises the non-volatile fuses turning on a predetermined quantity of transistors in response to the first data.  
   
   
       16 . The method of  claim 15  wherein each of the predetermined quantity of transistors couples a capacitor to the signal propagation path.  
   
   
       17 . The method of  claim 12  wherein the first data indicates the amount of time delay to add to the signal propagation path.  
   
   
       18 . The method of  claim 12  wherein the first data comprises a predetermined pattern that selectively turns on transistors, each transistor coupling a capacitor to the signal propagation path.