Integrated circuit assemblies and assembly methods

Abstract

A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, the method includes removing oxide from bumps, applying no-flow underfill to a substrate, and fluxlessly connecting the bumps to pads on the substrate. In an embodiment, oxide is removed from the bumps by a plasma treatment. In an embodiment, oxide is removed from the bumps by a subjecting the bumps to an oxide reduction process. The assembly of the chips and substrate is free from flux residue and/or flux cleaning solution residue.

1 . An assembly, comprising: 
 a die having a plurality of die interconnects;    a substrate having a plurality of substrate interconnects that are joined to the die interconnects to form flux-free joints;    a void intermediate the joints, the die, and the substrate;    a flux-free, no-flow underfill in the void; and    wherein the void is free of flux cleaning residue.    
   
   
       2 . The assembly of  claim 1 , wherein the joints have a height on the order of about a nanometer.  
   
   
       3 . The assembly of  claim 1 , wherein the plurality of die interconnects are plasma cleaned solder bumps.  
   
   
       4 . The assembly of  claim 3 , wherein the plurality of substrate interconnects are pads.  
   
   
       5 . The assembly of  claim 1 , wherein the plurality of substrate interconnects are plasma cleaned solder bumps.  
   
   
       6 . The assembly of  claim 5 , wherein the plurality of die interconnects are pads.  
   
   
       7 . An assembly, comprising: 
 a die having a die surface and a plurality of die interconnects on the die surface;    a substrate having a substrate surface and a plurality of substrate interconnects on the substrate surface, the plurality of substrate interconnects being joined to the die interconnects to form flux-free joints;    a void intermediate the joints, the die surface and the substrate surface, wherein the void has a height of less than about 100 microns; and    a flux-free, no-flow underfill in the void.    
   
   
       8 . The assembly of  claim 7 , wherein the void is free of flux cleaning residue.  
   
   
       9 . The assembly of  claim 7 , wherein the height of the void is greater than 75 microns.  
   
   
       10 . The assembly of  claim 7 , wherein the void has a maximum height of about 75 microns.  
   
   
       11 . The assembly of  claim 7 , wherein the plurality of die interconnects are plasma cleaned solder bumps.  
   
   
       12 . The assembly of  claim 11 , wherein the plurality of substrate interconnects are plasma cleaned solder bumps.  
   
   
       13 . An electrical system, comprising: 
 a user interface; and    an electrical circuit in communication with the user interface, the electrical circuit including an assembly comprising:    a die having a plurality of die interconnects;    a substrate having a plurality of substrate interconnects that are joined to the die interconnects to form flux-free joints;    a void intermediate the joints, the die and the substrate;    a flux-free, no-flow underfill in the void; and    wherein the void is free of flux cleaning residue.    
   
   
       14 . The electrical system of  claim 13 , wherein the user interface includes at least one of keyboard, mouse, pointing device, tuning dial, switch, pedal, and keypad.  
   
   
       15 . The electrical system of  claim 13 , wherein the plurality of substrate interconnects are plasma cleaned solder bumps.  
   
   
       16 . The electrical system of  claim 13 , wherein the plurality of die interconnects are plasma cleaned solder bumps.  
   
   
       17 . An electrical system, comprising: 
 a user interface; and    an electrical circuit in communication with the user interface, the electrical circuit including an assembly comprising: 
 a die having a die surface and a plurality of die interconnects on the die surface;  
 a substrate having a substrate surface and a plurality of substrate interconnects on the substrate surface, the plurality of substrate interconnects being joined to the die interconnects to form flux-free joints;  
 a void intermediate the joints, the die surface and the substrate surface, wherein the void has a height of less than about 100 microns; and  
 a flux-free, no-flow underfill in the void.  
   
   
   
       18 . The electrical system of  claim 17 , wherein the void is free of flux cleaning residue.  
   
   
       19 . The electrical system of  claim 17 , wherein the die includes a processor.  
   
   
       20 . The electrical system of  claim 17 , wherein the die includes a memory device.  
   
   
       21 . The electrical system of  claim 20 , wherein the memory device includes a DRAM or an SRAM.  
   
   
       22 . The electrical system of  claim 17 , wherein the substrate is a surface mount device.  
   
   
       23 . The electrical system of  claim 17 , wherein the flux-free, no-flow underfill includes at least one of an epoxy resin, a catalyst, and a hardener.  
   
   
       24 . The electrical system of  claim 17 , wherein the flux-free, no-flow underfill includes an organic acid-free underfill.