Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge

Abstract

A wafer for charge amount evaluation having a silicon substrate and p-type regions sandwiched between a first silicon oxide film and a SA-NSG film and surrounded by an undoped silicon film is prepared and subjected to a target process for which an amount of charge is to be evaluated. Then, etching is performed by using a BHF solution. By measuring an amount of etching in the p-type region, an amount of positive charge caused by the process in the wafer can be evaluated quantitatively in an easy and convenient manner.

1 . An apparatus for evaluating an amount of charge, the apparatus comprising: 
 a substrate having a substantially intrinsic undoped silicon layer;    p-type regions dotted as discrete islands in the undoped silicon layer; and    a first insulating layer provided over the undoped silicon layer and the p-type regions.    
   
   
       2 . The apparatus of  claim 1 , wherein a second insulating layer is provided in a region of the substrate located below the undoped silicon layer.  
   
   
       3 . The apparatus of  claim 2 , wherein the second insulating layer has a thickness not less than 1 nm and not more than 500 nm.  
   
   
       4 . The apparatus of  claim 1 , wherein the undoped silicon layer has a thickness not less than 10 nm and not more than 10 μm.  
   
   
       5 . The apparatus of  claim 1 , wherein a concentration of an impurity contained in the p-type regions is not less than 1×10 16  cm −3  and not more than 1×10 23  cm −3 .  
   
   
       6 . The apparatus of  claim 1 , wherein a concentration of an impurity contained in the undoped silicon layer is not more than 1×10 15  cm −3 .  
   
   
       7 . The apparatus of  claim 1 , wherein the first insulating film has a thickness not less than 1 nm and not more than 500 nm.  
   
   
       8 . The apparatus of  claim 1 , further comprising: 
 a third insulating layer composed of an insulating material and provided on a back surface of the semiconductor substrate.    
   
   
       9 . The apparatus of  claim 8 , wherein the third insulating layer has a thickness not less than 1 nm and not more than 500 nm.  
   
   
       10 . The apparatus of  claim 1 , further comprising: 
 a conductor film on the first insulating layer.    
   
   
       11 - 20 . (canceled)