Integrated circuit routing resource optimization algorithm for random port ordering

Abstract

A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.

1 . A method for routing an integrated circuit signal bus, comprising: 
 selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;    positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;    positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;    for each port of the primary block, placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and    for each port of each secondary block, placing a secondary connection extending orthogonally from one of the primary connections to that port.    
     
     
         2 . The method of  claim 1 , wherein the primary bus route essentially describes a straight line.  
     
     
         3 . The method of  claim 1 , wherein the primary bus route contains at least one change of direction.  
     
     
         4 . A computer system for routing an integrated circuit signal bus, comprising: 
 means for selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;    means for positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;    means for positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;    for each port of the primary block, means for placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and    for each port of each secondary block, means for placing a secondary connection extending orthogonally from one of the primary connections to that port.    
     
     
         5 . The computer system of  claim 4 , wherein the primary bus route essentially describes a straight line.  
     
     
         6 . The computer system of  claim 4 , wherein the primary bus route contains at least one change of direction.  
     
     
         7 . A program storage medium readable by a computer system, embodying a program executable by the computer system to perform method steps for routing an integrated circuit signal bus, the method steps comprising: 
 selecting a primary block from a plurality of blocks, each of the blocks having a plurality of ports to be connected to the signal bus, the remainder of the plurality of blocks being secondary blocks;    positioning the plurality of ports of the primary block so that no two ports of the primary block reside with a single routing track running parallel to the portion of a primary bus route residing closest to the primary block;    positioning the plurality of ports of each secondary block so that no two ports within each secondary block reside within a single routing track running perpendicular to the portion of the primary bus route residing closest to that secondary block;    for each port of the primary block, placing a primary connection over that port parallel to the primary bus route, each primary connection running substantially the length of the primary bus route; and    for each port of each secondary block, placing a secondary connection extending orthogonally from one of the primary connections to that port.    
     
     
         8 . The program storage medium of  claim 7 , wherein the primary bus route essentially describes a straight line.  
     
     
         9 . The program storage medium of  claim 7 , wherein the primary bus route contains at least one change of direction.  
     
     
         10 . An integrated circuit signal bus structure, comprising: 
 a plurality of primary connections, each primary connection being connected to a separate port of a primary block, the plurality of primary connections lying essentially parallel to each other; and    a plurality of secondary connections, each secondary connection coupling a port of a secondary block with one of the plurality of primary connections, the connection between each secondary connection and its associated primary connection being perpendicular, the secondary connections of any single secondary block being parallel to each other.    
     
     
         11 . The integrated circuit signal bus structure of  claim 10 , wherein the plurality of primary connections essentially describes a straight line.  
     
     
         12 . The integrated circuit signal bus structure of  claim 10 , wherein the plurality of primary connections contains at least one change of direction.  
     
     
         13 . An integrated circuit containing the integrated circuit bus structure of  claim 10.