Method and apparatus for accessing a multi ordered memory array

Abstract

A method and system for transferring data in a multi ordered memory array from a source memory array to a destination memory array, at least one of which is multi-ordered. A reading memory access unit reads data from the source memory array according to a source access template and a writing memory access unit writes the data to the destination memory array according to a destination access template.

1 . A method for accessing a multi ordered memory array using a single channel, the method comprising: 
 determining an access template for accessing n (n>0) orders in the memory array; and    accessing said memory array according to said access template.    
   
   
       2 . The method according to  claim 1 , wherein said memory array is a source memory array having data that are read during said accessing.  
   
   
       3 . The method according to  claim 1 , wherein said memory array is a destination memory array having data that are written during said accessing.  
   
   
       4 . The method according to  claim 1  wherein said access template comprises: 
 a number (n) indicating how many orders (O i  for i=0, . . . , n−1) are to be accessed in said memory array;    an order offset (OOf 0 ) of a first order O 0  of said orders;    a respective order size (S i ) of said orders O i  (where i=1, . . . , n−1); and    a respective order gap offset (GOf i ) of said orders O i  (where i=0,1, . . . , n−1).    
   
   
       5 . The method according to  claim 1  wherein n=3.  
   
   
       6 . A method for transferring data by a memory controller from a source array to a destination array, the method comprising: 
 determining a source access template for reading n orders from said source memory array;    determining a destination access template for writing m orders to said destination memory array;    reading data from said source memory array according to said source access template; and    writing data to said destination memory array according to said destination access template;    where at least one of n or m>0.    
   
   
       7 . The method according to  claim 6  wherein the memory controller is a Direct Memory Access (DMA) controller.  
   
   
       8 . The method according to claims  6  wherein said source access template comprises: 
 a number (n) indicating how many orders O i  (where i=0, . . . , n−1) are to be read from said source memory array;    a source order offset (OOf 0 ) of a first order O 0  of said orders;    a respective source order size (S i ) of said orders O i  (where i=1, . . . , n); and    a respective source order gap offset (GOf i ) of said orders O i  (where i=0,1, . . . , n−1).    
   
   
       9 . The method according to  claim 8  wherein the memory controller is a Direct Memory Access (DMA) controller.  
   
   
       10 . The method according to claims  6  wherein said destination access template comprises: 
 a number (m) indicating how many orders O i  (where i=0, . . . , m−1) are to be written to said destination memory array;    a destination order offset (OOf 0 ) of a first order O 0  of said orders;    a respective destination order size (S i ) of said orders O i  (where i=1, . . . , m); and    a respective destination order gap offset (GOf i ) of said orders O i  (where i=0,1, . . . , m−1).    
   
   
       11 . The method according to  claim 10  wherein the memory controller is a Direct Memory Access (DMA) controller.  
   
   
       12 . The method according to  claim 6  wherein said source access template is substantially similar to said destination access template.  
   
   
       13 . A memory access unit for accessing a multi ordered memory array using a single channel, the access controller comprising: 
 access configuring registers for storing access parameters being part of an access template, said access template allowing accessing n orders in the memory array; and    an access controller coupled to said access configuration registers for accessing said memory array according to said access template.    
   
   
       14 . A transfer controller for transferring data in a memory controller from a source memory array to a destination memory array, the transfer controller comprising: 
 a reading memory access unit for reading data from said source memory array according to a source access template; and    a writing memory access unit for writing data to said destination memory array according to a destination access template.    
   
   
       15 . The transfer controller according to  claim 14  wherein the memory controller is a Direct Memory Access (DMA) controller.  
   
   
       16 . The transfer controller according to  claim 14  further comprising: 
 a buffer coupled to said reading memory access unit and said writing memory access unit, said reading memory access unit conveying data from said source memory array to said buffer and said writing memory access unit conveying data from said buffer to said destination memory array.    
   
   
       17 . The transfer controller according to  claim 16  wherein the memory controller is a Direct Memory Access (DMA) controller.