Bounding data transmission latency based upon link loading and arrangement

Abstract

A method, apparatus, system, and machine-readable medium to bound data transmission latency by transmitting error verification data at a point during a data transmission based upon loading of a channel for the data transmission is provided. Embodiments may comprise determining the loading of a communication channel and transmitting error verification data to a target device based upon the loading. More specifically, some embodiments transmit error verification data at intervals, variable intervals in some embodiments, to balance transmission latency against the bandwidth available from a communication medium.

1 . An apparatus, comprising: 
 a queue to receive data from a transaction layer to transmit across a channel of a communication medium;    load monitor circuitry coupled with said queue to determine a loading of the channel;    logic circuitry coupled with said load monitor circuitry to determine a point during a data transmission to transmit error verification data based upon the loading; and    verification circuitry coupled with said logic circuitry, to transmit the error verification data near the point.    
   
   
       2 . The apparatus of  claim 1 , further comprising physical layer circuitry coupled with the data transmission queue, to transmit data across the communication medium.  
   
   
       3 . The apparatus of  claim 1 , wherein said queue comprises a first-in, first-out queue.  
   
   
       4 . The apparatus of  claim 3 , wherein said queue comprises a random-access data storage queue.  
   
   
       5 . The apparatus of  claim 1 , wherein said load monitor circuitry comprises queue fullness circuitry to monitor an amount of data in said queue.  
   
   
       6 . The apparatus of  claim 5 , wherein the queue fullness circuitry comprises a counter coupled with said verification circuitry, to count data units received by said queue.  
   
   
       7 . The apparatus of  claim 1 , wherein said logic circuitry comprises: 
 a counter coupled with said queue to count data units to transmit;    a multiplexer to select a target number of data units; and    a comparator coupled with the counter to compare the count of unprotected data units against the target number of data units to be selected by the multiplexer.    
   
   
       8 . The apparatus of  claim 1 , wherein said logic circuitry comprises circuitry to select the point during the data transmission based upon a heuristically-chosen target.  
   
   
       9 . The apparatus of  claim 1 , wherein said logic circuitry comprises circuitry to determine a number of unprotected data units to transmit between transmissions of error verification data.  
   
   
       10 . The apparatus of  claim 1 , wherein said verification circuitry comprises circuitry to generate a checksum.  
   
   
       11 . The apparatus of  claim 10 , wherein said verification circuitry comprises circuitry to transmit the checksum.  
   
   
       12 . The apparatus of  claim 1 , wherein said verification circuitry comprises circuitry to monitor a running disparity of the data transmission.  
   
   
       13 . The apparatus of  claim 12 , wherein said verification circuitry comprises circuitry to transmit a symbol to cause a transition in the running disparity of the data transmission.  
   
   
       14 . A method, comprising: 
 receiving data from a transaction layer to transmit across a channel of a communication medium;    determining a loading of the channel based upon said receiving data;    determining a point during a data transmission to transmit error verification data based upon the loading; and    transmitting the error verification data substantially at the point.    
   
   
       15 . The method of  claim 14 , wherein said receiving comprises receiving packetized data.  
   
   
       16 . The method of  claim 14 , wherein said determining a loading comprises monitoring an amount of data in a data transmission queue.  
   
   
       17 . The method of  claim 14 , wherein said determining a point comprises determining a target number of unprotected data units to transmit before said transmitting error verification data.  
   
   
       18 . The method of  claim 14 , wherein said determining a point comprises determining a target location in the data transmission based upon a heuristically-chosen target.  
   
   
       19 . The method of  claim 14 , wherein said transmitting the error verification data comprises: 
 counting a number of unprotected data units transmitted; and    comparing the number of data units transmitted against a target number of unprotected data units.    
   
   
       20 . The method of  claim 14 , wherein said transmitting the error verification data comprises selecting a symbol to cause a transition in a running disparity.  
   
   
       21 . The method of  claim 14 , wherein said transmitting the error verification data comprises generating a checksum.  
   
   
       22 . A system, comprising: 
 a memory device;    a memory controller coupled with said memory device to provide access to memory contents of said memory device; and    an input-output controller coupled with said memory controller to access the memory contents, comprising 
 a queue to receive data from a transaction layer to transmit across a channel of a communication medium;  
 load monitor circuitry coupled with said queue to determine a loading of the channel;  
 logic circuitry coupled with said load monitor circuitry to determine a point during a data transmission to transmit the error verification data based upon the loading; and  
 verification circuitry coupled with the logic circuitry, to transmit the error verification data near the point.  
   
   
   
       23 . The system of  claim 21 , further comprising a processor coupled with said input-output controller to communicate with an agent coupled with the communication medium.  
   
   
       24 . The system of  claim 21 , wherein verification circuitry comprises circuitry to transmit a symbol to cause a transition in a running disparity of the data transmission.  
   
   
       25 . A system, comprising: 
 a first input-output device to initiate a request for data via a communication medium;    a second input-output device coupled with said first input-output device to respond to the request with the data, comprising 
 a queue to store data from transaction layer circuitry to transmit across a channel of a communication medium;  
 load monitor circuitry coupled with said queue to determine a loading of the channel;  
 logic circuitry coupled with said load monitor circuitry to determine a point during a data transmission to transmit error verification data based upon the loading; and  
 verification circuitry coupled with the logic circuitry, to transmit error verification data near the point; and  
   a processor coupled with said second input-output device to respond to the request for data.    
   
   
       26 . The system of  claim 25 , wherein said second input-output device further comprises a switch to couple a third input-output device with said processor.  
   
   
       27 . The system of  claim 25 , wherein said first input-output device comprises a switch to couple a fourth input-output device with said processor.  
   
   
       28 . A machine-readable medium containing instructions, which when executed by a machine, cause said machine to perform operations, comprising: 
 receiving data from a transaction layer to transmit across a channel of a communication medium;    determining a loading of the channel based upon said receiving data;    determining a point during a data transmission to transmit error verification data based upon the loading; and    transmitting the error verification data substantially at the point.    
   
   
       29 . The machine-readable medium of  claim 28 , wherein said transmitting the error verification data comprises selecting a symbol to cause a transition in a running disparity.  
   
   
       30 . The machine-readable medium of  claim 28 , wherein said transmitting the error verification data comprises generating a checksum.