Synchronous flash memory

Abstract

A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.

1 . A computer system comprising: 
 a memory controller; and    a synchronous non-volatile memory device coupled to the memory controller, wherein the synchronous non-volatile memory device has a plurality of external connections which are physically arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).    
   
   
       2 . The computer system of  claim 1 , wherein the plurality of external connections are one of a plurality of interconnect pins and solder bump connections.  
   
   
       3 . The computer system of  claim 1 , wherein the synchronous non-volatile memory device further comprises a command interface comprising: 
 a write enable connection (WE#) to receive a write enable signal;    a column address strobe connection (CAS#) to receive a column address strobe signal;    a row address strobe connection (RAS#) to receive a row address strobe signal; and    a chip select connection (CS#) to receive a chip select signal.    
   
   
       4 . The computer system of  claim 1 , wherein the synchronous non-volatile memory further comprises a reset connection (RP#), and a Vccp power supply connection that correspond to first and second no-connect (NC) connections of the synchronous dynamic random access memory (SDRAM).  
   
   
       5 . The computer system of  claim 1 , wherein the synchronous non-volatile memory device is adapted to operate within read timing specification parameters for a synchronous dynamic random access memory (SDRAM).  
   
   
       6 . The computer system of  claim 1 , wherein the synchronous non-volatile memory device is one of a synchronous flash memory device and a synchronous EEPROM memory device.  
   
   
       7 . The computer system of  claim 1 , further comprising a package and external connections compatible with synchronous dynamic random access memory (SDRAM) specifications.  
   
   
       8 . The computer system of  claim 1 , wherein the plurality of external connections further comprise: 
 a plurality of bi-directional data connections;    a plurality of memory address connections;    a clock input connection;    a clock enable connection;    a plurality of memory array bank address connections;    power supply connections;    a plurality of data mask connections;    a reset connection; and    a Vccp power supply connection.    
   
   
       9 . A synchronous non-volatile memory device comprising: 
 an array of non-volatile memory cells; and    a package having a plurality of external connections arranged in a manner that corresponds to the external connections of a synchronous dynamic random access memory device (SDRAM).    
   
   
       10 . The synchronous non-volatile memory device of  claim 9 , wherein the plurality of external connections are one of a plurality of interconnect pins and solder bump connections.  
   
   
       11 . The synchronous non-volatile memory device of  claim 9 , further comprising a command interface comprising: 
 a write enable connection (WE#) to receive a write enable signal;    a column address strobe connection (CAS#) to receive a column address strobe signal;    a row address strobe connection (RAS#) to receive a row address strobe signal; and    a chip select connection (CS#) to receive a chip select signal.    
   
   
       12 . The synchronous non-volatile memory device of  claim 9 , further comprising a reset connection (RP#), and a Vccp power supply connection that correspond to first and second no-connect (NC) connections of the synchronous dynamic random access memory (SDRAM).  
   
   
       13 . The synchronous non-volatile memory device of  claim 9 , wherein the synchronous non-volatile memory device is adapted to operate within read timing specification parameters for a synchronous dynamic random access memory (SDRAM).  
   
   
       14 . The synchronous non-volatile memory device of  claim 9 , wherein the synchronous non-volatile memory device is one of a synchronous flash memory device and a synchronous EEPROM memory device.  
   
   
       15 . The synchronous non-volatile memory device of  claim 9 , further comprising a package compatible with a synchronous dynamic random access memory (SDRAM) specification.  
   
   
       16 . The synchronous non-volatile memory device of  claim 9 , wherein the plurality of external connections further comprise: 
 a plurality of bi-directional data connections;    a plurality of memory address connections;    a clock input connection;    a clock enable connection;    a plurality of memory array bank address connections;    power supply connections;    a plurality of data mask connections;    a reset connection; and    a Vccp power supply connection.    
   
   
       17 . A synchronous non-volatile memory device having an interface comprising: 
 a plurality of external connections, wherein the plurality of external connections are arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).    
   
   
       18 . The synchronous non-volatile memory device of  claim 17 , further comprising: 
 a clock input connection to receive a clock signal;    a write enable connection to receive a write enable signal;    a column address strobe connection to receive a column address strobe signal;    a row address strobe connection to receive a row address strobe signal;    a chip select connection to receive a chip select signal;    a reset connection to receive a reset signal; and    a Vccp power supply connection to receive an elevated power supply signal.    
   
   
       19 . The synchronous non-volatile memory device of  claim 17 , wherein the interface further comprises: 
 a plurality of bi-directional data connections;    a plurality of memory address connections;    a clock enable connection;    a plurality of memory array bank address connections;    power supply connections; and    a plurality of data mask connections.    
   
   
       20 . The synchronous non-volatile memory device of  claim 17 , further comprising a package having a plurality of interconnect pins or solder bump connections corresponding to the plurality of external connections.  
   
   
       21 . The synchronous non-volatile memory device of  claim 17 , wherein the interface of the synchronous non-volatile memory device is adapted to operate within read timing specification parameters for a synchronous dynamic random access memory (SDRAM).  
   
   
       22 . The synchronous non-volatile memory device of  claim 17 , further comprising a reset connection (RP#), and a Vccp power supply connection that correspond to first and second no-connect (NC) connections of the synchronous dynamic random access memory (SDRAM).