Split gate flash memory cell with ballistic injection

Abstract

A split floating gate flash memory cell is comprised of source/drain regions in a substrate. The split floating gate is insulated from the substrate by a first layer of oxide material and from a control gate by a second layer of oxide material. The sections of the floating gate are isolated from each other by a depression in the control gate. The cell is programmed by creating a positive charge on the floating gate and biasing the drain region while grounding the source region. This creates a virtual source/drain region near the drain region such that the hot electrons are accelerated in the narrow pinched off region. The electrons become ballistic and are directly injected onto the floating gate section adjacent to the pinched off channel region.

1 . A flash memory cell comprising: 
 a substrate having a pair of doped regions, the pair of doped regions being linked by a channel in the substrate;    a split floating gate comprising a plurality of sections such that a first floating gate section establishes a virtual source/drain region in the channel, the virtual source/drain region having a lower threshold voltage than a remaining portion of the channel; and    a control gate formed over the split floating gate and comprising a depression formed between the plurality of sections such that the depression electrically isolates the floating gate sections.    
   
   
       2 . The cell of  claim 1  wherein the split floating gate is in a vertical configuration.  
   
   
       3 . The cell of  claim 1  and further including a substrate bias connection that is capable of applying a bias to the substrate.  
   
   
       4 . The cell of  claim 3  wherein the bias is in a range of −1V to −2V.  
   
   
       5 . The cell of  claim 2  wherein the channel between the vertical split floating gate sections is two-dimensional.  
   
   
       6 . The cell of  claim 1  wherein the virtual source/drain region is established in response to an absence of electrons on the first floating gate section.  
   
   
       7 . The cell of  claim 1  wherein the substrate is a p-type silicon material and the doped regions are an n-type silicon material.  
   
   
       8 . A flash memory cell comprising: 
 a substrate having a pair of source/drain regions, the pair of source/drain regions being linked by a channel;    a planar split floating gate comprising a plurality of floating gate sections such that a first floating gate section establishes a virtual source/drain region in the channel, the virtual source/drain region having a lower threshold voltage than a remaining portion of the channel; and    a control gate formed over the planar split floating gate and comprising a depression formed between the plurality of floating gate sections such that the depression electrically isolates the floating gate sections.    
   
   
       9 . The cell of  claim 7  wherein the virtual source/drain region is established in response to a drain voltage being applied to a first source/drain region adjacent the virtual source/drain region.  
   
   
       10 . The cell of  claim 8  and further including a first oxide layer between the substrate and the planar split floating gate and a second oxide layer between the planar split floating gate and the control gate.  
   
   
       11 . The cell of  claim 8  wherein the virtual source/drain region has a length in a range of 10-40 nm.  
   
   
       12 . The cell of  claim 8  wherein the virtual source/drain region is established in response to a positive charge on the first floating gate section.  
   
   
       13 . A flash memory cell comprising: 
 a substrate having a pair of source/drain regions, each source/drain region located under a trench in the substrate, the pair of source/drain regions being linked by a two-dimensional channel that follows a surface of a pillar formed between the trenches;    a vertical split floating gate comprising a plurality of floating gate sections that are separated by the pillar, a first floating gate section capable of establishing a virtual source/drain region in the channel adjacent to the first floating gate, the virtual source/drain region having a lower threshold voltage than a remaining portion of the channel; and    a control gate formed over the vertical split floating gate.    
   
   
       14 . The cell of  claim 13  wherein a depression of the control gate is formed in the trench to separate a first flash memory cell from a second flash memory cell.  
   
   
       15 . The cell of  claim 13  wherein the virtual source/drain region is 100-400 Å in length.  
   
   
       16 . The cell of  claim 13  wherein the source/drain regions link a plurality of memory cells in a virtual ground array configuration.  
   
   
       17 . A flash memory cell array comprising: 
 a plurality of memory cells coupled together through wordlines and bitlines, each cell comprising: 
 a substrate having a pair of source/drain regions, the pair of source/drain regions being linked by a channel in the substrate, each source/drain region coupled to a different bitline;  
 a split floating gate comprising a plurality of sections such that a first floating gate section establishes a virtual source/drain region in the channel adjacent to the first floating gate section, the virtual source/drain region having a lower threshold voltage than a remaining portion of the channel; and  
 a control gate formed over the split floating gate and comprising a depression formed between the plurality of sections such that the depression electrically isolates the floating gate sections, the control gate coupled to the wordlines.  
   
   
   
       18 . The array of  claim 17  wherein the plurality of memory cells are configured in a NAND-type architecture.  
   
   
       19 . The array of  claim 17  wherein the plurality of memory cells are configured in a NOR-type architecture.  
   
   
       20 . An electronic system comprising: 
 a processor that generates memory control signals; and    a flash memory cell array coupled to the processor and comprising a plurality of memory cells coupled together through wordlines and bitlines, each cell comprising: 
 a substrate having a pair of source/drain regions, the pair of source/drain regions being linked by a channel in the substrate, each source/drain region coupled to a different bitline;  
 a split floating gate comprising a plurality of sections such that a first floating gate section establishes a virtual source/drain region in the channel adjacent to the first floating gate section, the virtual source/drain region having a lower threshold voltage than a remaining portion of the channel; and  
 a control gate formed over the split floating gate and comprising a depression formed between the plurality of sections such that the depression electrically isolates the floating gate sections, the control gate coupled to the wordlines.  
   
   
   
       21 . A method for writing to a flash memory cell comprising a split floating gate located between a substrate having two source/drain regions and a control gate, the two source/drain regions linked by a channel in the substrate, the method comprising: 
 creating a positive charge on the floating gate;    grounding a first source/drain region;    applying a gate voltage to the control gate; and    applying a drain voltage to the second source/drain region such that ballistic direction injection occurs in a virtual source/drain region of the channel adjacent a section of the split floating gate.    
   
   
       22 . The method of  claim 21  and further including applying a substrate bias to the substrate.  
   
   
       23 . The method of  claim 22  wherein the substrate bias is a negative voltage.  
   
   
       24 . The method of  claim 21  wherein creating the positive charge includes overerasing the flash memory cell.  
   
   
       25 . A method for writing to a flash memory cell comprising a split floating gate located between a substrate having two source/drain regions and a control gate, the two source/drain regions linked by a channel in the substrate, the method comprising: 
 creating a positive charge on the floating gate;    grounding a first source/drain region;    applying a gate voltage to the control gate; and    applying a drain voltage to the second source/drain region such that the channel is pinched off a distance in a range of 10-40 nm from the second source/drain region and adjacent to a section of the split floating gate.