Adhesive/spacer island structure for multiple die package

Abstract

An adhesive/spacer structure ( 52, 52 A, 60 ) is used to adhere first and second die ( 14, 18 ) to one another at a chosen separation in a multiple-die semiconductor chip package ( 56 ). The first and second die define a die bonding region ( 38 ) therebetween. The adhesive/spacer structure may comprise a plurality of spaced-apart adhesive/spacer islands ( 52, 52 A) securing the first and second die to one another at a chosen separation ( 53 ). The adhesive/spacer structure may also secure the first and second die to one another to occupy about 1-50% of the die bonding region.

1 . An adhesive/spacer structure used to adhere first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the adhesive/spacer structure comprising: 
 a plurality of spaced-apart adhesive/spacer islands securing the first and second die to one another at a chosen separation; and    said adhesive/spacer islands comprising an adhesive/spacer material, said adhesive/spacer material comprising deformable spacer elements embedded within adhesive.    
     
     
         2 . The structure according to  claim 1  comprising at least three of said spaced-apart adhesive/spacer islands.  
     
     
         3 . The structure according to  claim 1  wherein at least one of said adhesive/spacer islands comprises a plurality of said spacer elements.  
     
     
         4 . The structure according to  claim 1  wherein the spacer elements are all substantially the same size.  
     
     
         5 . The structure according to  claim 1  wherein the spacer elements comprise generally ellipsoidal spacer elements.  
     
     
         6 . The structure according to  claim 5  wherein the generally ellipsoidal spacer elements comprise flattened generally spherical spacer elements.  
     
     
         7 . The structure according to  claim 1  wherein the spacer elements are deformable polymer spacer elements.  
     
     
         8 . The structure according to  claim 7  wherein the deformable polymer spacer elements comprise PTFE.  
     
     
         9 . The structure according to  claim 1  wherein each of the adhesive/spacer islands are about the same size.  
     
     
         10 . The structure according to  claim 1  wherein a first of the adhesive/spacer islands is at least twice the size of a second of the adhesive/spacer islands.  
     
     
         11 . A multiple-die semiconductor chip package comprising: 
 a substrate;    a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;    wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;    a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer;    a plurality of spaced-apart adhesive/spacer islands within the die bonding region securing the first and second die to one another at a chosen separation to create a multiple-die subassembly, the adhesive/spacer islands occupying a first percentage of the die bonding region;    the adhesive/spacer islands comprising at least one spacer element within an adhesive; and    a material encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.    
     
     
         12 . The package according to  claim 11  wherein the first percentage is between about 20-50 percent.  
     
     
         13 . The package according to  claim 11  wherein the first percentage is at most about 50%.  
     
     
         14 . The package according to  claim 11  wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100 percent thereby effectively eliminating voids within the die bonding region.  
     
     
         15 . The package according to  claim 11  wherein: 
 the adhesive comprises epoxy; and    the encapsulating material comprises a filled epoxy.    
     
     
         16 . The package according to  claim 11  wherein the adhesive and the encapsulating material create an adhesive/encapsulating material boundary within the die bonding region.  
     
     
         17 . An adhesive/spacer structure used to adhere opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the multiple-die semiconductor chip package comprising the first and second die defining a die bonding region therebetween, the adhesive/spacer structure comprising: 
 adhesive/spacer structure comprising spacer elements within an adhesive, the spacer elements comprising a deformable material; and    the adhesive/spacer structure securing the first and second die to one another and occupying at most about 50% of the die bonding region.    
     
     
         18 . The structure according to  claim 17  wherein the adhesive/spacer structure comprises first and second adhesive/spacer structures spaced apart from one another.  
     
     
         19 . The structure according to  claim 17  wherein the adhesive/spacer structure comprises at least three adhesive/spacer structures spaced apart from one another.  
     
     
         20 . The structure according to  claim 17  wherein the adhesive/spacer structure occupies about 20-50% of the die bonding region.  
     
     
         21 . A multiple-die semiconductor chip package comprising: 
 a substrate;    a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;    wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;    a second die with a second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer;    adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die subassembly;    the adhesive/spacer structure comprising spacer elements within an adhesive;    the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%; and    a material encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.    
     
     
         22 . The package according to  claim 21  wherein the first percentage is about 20-50%.  
     
     
         23 . The package according to  claim 21  wherein the wires within the die bonding region occupy a third percentage of the die bonding region, and wherein the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.  
     
     
         24 . A method for adhering first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: 
 selecting an adhesive/spacer material having spacer elements within an adhesive;    depositing the adhesive/spacer material onto a first surface of a first die at a plurality of spaced-apart positions;    providing a second surface of the second die with a dielectric layer;    locating the second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: 
 securing the first and second die to one another at a chosen separation; and  
   the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step.    
     
     
         25 . The method according to  claim 24  wherein the selecting step comprises choosing spacer elements having the same size and shape.  
     
     
         26 . The method according to  claim 24  wherein the depositing step is carried out to create a plurality of generally equal-size islands of the adhesive/spacer material after the securing step.  
     
     
         27 . The method according to  claim 24  wherein the depositing step is carried out to create at least three generally equal-size islands of the adhesive/spacer material after the securing step.  
     
     
         28 . A method for creating a multiple-die semiconductor chip package, the method comprising: 
 mounting a first die to a substrate, the first die having a first surface with bond pads at the first surface;    connecting the bond pads and the substrate with wires;    selecting an adhesive/spacer material comprising spacer elements within an adhesive;    depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions;    providing a second surface of the second die with a dielectric layer;    locating a second surface of a second die opposite the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: 
 defining a die bonding region between the first and second surfaces; and  
 securing the first and second die to one another at a chosen separation to create a multiple-die subassembly;  
   the selecting and depositing steps carried out to create a plurality of spaced-apart adhesive/spacer islands following the securing step, the adhesive/spacer islands occupying a first percentage of the die bonding region; and    encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.    
     
     
         29 . The method according to  claim 28  wherein the depositing step is carried out so that the first percentage is about 20-50 percent.  
     
     
         30 . The method according to  claim 28  wherein the depositing step is carried out so that the first percentage is at most about 50%.  
     
     
         31 . The method according to  claim 28  wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.  
     
     
         32 . A method for adhering opposed surfaces of first and second die to one another at a chosen separation in a multiple-die semiconductor chip package, the method comprising: 
 selecting an adhesive/spacer material having spacer elements within an adhesive;    choosing an amount of the adhesive/spacer material;    depositing the chosen amount the adhesive/spacer material onto a first surface of a first die;    providing a second surface of the second die with a dielectric layer;    locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: 
 defining a die bonding region between the first and second surfaces; and  
 securing the first and second die to one another at a chosen separation; and  
   the choosing and depositing steps carried out so that the adhesive/spacer material occupies at most about 50% of the die bonding region following the securing step.    
     
     
         33 . The method according to  claim 32  wherein the depositing step is carried out to create a single, continuous expanse of the adhesive/spacer material after the securing step.  
     
     
         34 . The method according to  claim 32  wherein the choosing step is carried out so that the adhesive/spacer material occupies about 20-50% of the die bonding region.  
     
     
         35 . A method for creating a multiple-die semiconductor chip package, the method comprising: 
 mounting a first die to a substrate, the first die comprising a first surface with bond pads at the first surface;    connecting the bond pads and the substrate with wires;    selecting an adhesive/spacer material having spacer elements within an adhesive;    depositing the adhesive/spacer material onto a first surface of the first die at a plurality of spaced-apart positions;    locating a second surface of a second die opposite at the first surface of the first die and in contact with the adhesive/spacer material therebetween thereby: 
 defining a die bonding region between the first and second surfaces; and  
 securing the first and second die to one another at a chosen separation to create a multiple-die subassembly;  
   the selecting and depositing steps carried out so that the adhesive/spacer material occupies a first percentage of the die bonding region, the first percentage being at most about 50%; and    encapsulating the multiple-die subassembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region, and the wires within the die bonding region occupying a third percentage of the die bonding region.    
     
     
         36 . The method according to  claim 35  wherein the depositing step is carried out so that the first percentage is about 20-50%.  
     
     
         37 . The method according to  claim 35  wherein, the sum of the first, second and third percentages is about 100% thereby effectively eliminating voids within the die bonding region.