Memory device having an electron trapping layer in a high-K dielectric gate stack

Abstract

An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

1 . A semiconductor memory device comprising: 
 a semiconductor substrate;    a dielectric gate stack formed on a channel region of the substrate, the dielectric gate stack having a top portion and a bottom portion with a gate electrode formed on the top portion;    the dielectric gate stack including electron trapping material consisting of an electron trapping material selected from zirconium oxide and aluminum oxide; and    a gate electrode connected with the top portion of the gate stack.    
   
   
       2 : The semiconductor memory device of  claim 1  wherein the electron trapping material is further selected from hafnium oxide.  
   
   
       3 . The semiconductor memory device of  claim 2  wherein the top portion and the bottom portion of the dielectric gate stack are comprised entirely of the electron trapping material.  
   
   
       4 - 9 . (canceled)  
   
   
       10 : A semiconductor integrated circuit having the semiconductor memory devices of  claim 3  formed thereon.  
   
   
       11 . (canceled)  
   
   
       12 : A method for forming a memory device comprising: 
 providing a semiconductor substrate;    forming a gate stack over a channel region of the substrate such that the gate stack includes a layer of electron trapping material; and    forming a gate electrode connected with a top portion of the gate stack.    
   
   
       13 : The method for forming a memory device as in  claim 12 , wherein forming the layer of electron trapping material comprises formed the layer of electron trapping material with a material selected from among the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide.  
   
   
       14 : The method for forming a memory device as in  claim 12  wherein forming the gate stack comprises forming a first layer of dielectric material over the channel region of the substrate and forming the layer of electron trapping material over the first layer of dielectric material and forming a gate electrode connected with the layer of electron trapping material.  
   
   
       15 : The method for forming a memory device as in  claim 14 , wherein forming the layer of electron trapping material comprises formed the layer of electron trapping material with a material selected from among the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide.  
   
   
       16 : The method for forming a memory device as in  claim 15 , wherein forming the first layer of dielectric material comprises formed the first layer of dielectric material with a silicon oxide material.  
   
   
       17 : The method for forming a memory device as in  claim 12  wherein forming the gate stack comprises: 
 forming a first layer of dielectric material over the channel region of the substrate;    forming the layer of electron trapping material over the first layer of dielectric material;    forming a second layer of dielectric material over the layer of electron trapping material; and    forming a gate electrode connected with a top portion of the second layer of dielectric material.    
   
   
       18 : A method for forming a memory device as in  claim 17 , wherein forming the layer of electron trapping material comprises formed the layer of electron trapping material with a material selected from among the group consisting of zirconium oxide, hafnium oxide, and aluminum oxide.  
   
   
       19 : The method for forming a memory device as in  claim 18 , wherein forming the first layer of dielectric material and forming the second layer of dielectric material comprises formed the first layer of dielectric material and the second layer of dielectric material with a silicon oxide material.  
   
   
       20 : The method for forming a memory device as in  claim 18 , wherein forming the first layer of dielectric material and forming the second layer of dielectric material comprises formed the first layer of dielectric material and the second layer of dielectric material with different dielectric material.  
   
   
       21 . The semiconductor memory device of  claim 3  wherein the gate electron includes an upper diffusion region that includes electron trapping material diffused from the top portion of the dielectric gate stack and wherein the channel region of the substrate includes a lower diffusion region that includes electron trapping material diffused from the bottom portion of the dielectric gate stack.  
   
   
       22 . The semiconductor memory device of  claim 21  wherein the upper and lower diffusion regions comprise Zr x Si y O z  material.  
   
   
       23 . The semiconductor memory device of  claim 21  wherein the upper and lower diffusion regions comprise Al x Si y O z  material.  
   
   
       24 . The semiconductor memory device of  claim 21  wherein the upper and lower diffusion regions comprise Hf x Si y O z  material.  
   
   
       25 . The semiconductor memory device of  claim 1  wherein a dielectric layer is formed adjacent to the channel region at the bottom portion of the dielectric stack so that the dielectric layer lies between the channel region and the electron trapping material.