Controlling execution of a block of program instructions within a computer processing system

Abstract

A data processing apparatus and method are disclosed. The data processing apparatus comprises: an instruction fetching circuit operable to fetch a sequence of program instructions from a sequence of memory locations; an instruction decoder responsive to program instructions within the sequence of program instructions fetched by the instruction fetching circuit to control data processing operations specified by the program instructions; and an execution circuit operable under control of the instruction decoder to execute the data processing operations, wherein the instruction decoder is responsive to an execute block instruction within the sequence of program instructions to trigger fetching of a block of two or more program instructions by the instruction fetching circuit and execution of the block of two or more program instructions by the execution circuit, the block of two or more instructions containing a number of program instructions specified by a block length field within the executed block instruction and being stored at a memory location specified by a location field within the execute block instruction, the apparatus further comprises execute block instruction logic operable in response to the execute block instruction to store an indication of a memory location of an instruction following the execute block instruction and to determine which instruction in the block of two or more program instructions is being processed, the execute block instruction logic being further operable when it is determined that a last instruction in the block of two or more program instructions is being processed to provide to the instruction fetching circuit the indication of the memory location of the instruction following the execute block instruction so that the instruction following the execute block instruction is fetched for execution immediately following the last instruction in the block of two or more program instructions. Providing the indication of the memory location of the instruction following the execute block instruction to the instruction fetching circuit causes the fetch unit to fetch that instruction so that the correct sequence of instructions is fetched by the fetch unit which avoids the need to flush instructions.

1 . A data processing apparatus comprising: 
 an instruction fetching circuit operable to fetch a sequence of program instructions from a sequence of memory locations;    an instruction decoder responsive to program instructions within said sequence of program instructions fetched by said instruction fetching circuit to control data processing operations specified by said program instructions; and    an execution circuit operable under control of said instruction decoder to execute said data processing operations, wherein said instruction decoder is responsive to an execute block instruction within said sequence of program instructions to trigger fetching of a block of two or more program instructions by said instruction fetching circuit and execution of said block of two or more program instructions by said execution circuit, said block of two or more instructions containing a number of program instructions specified by a block length field within said executed block instruction and being stored at a memory location specified by a location field within said execute block instruction, said apparatus further comprising    execute block instruction logic operable in response to said execute block instruction to store an indication of a memory location of an instruction following said execute block instruction and to determine which instruction in said block of two or more program instructions is being processed, said execute block instruction logic being further operable when it is determined that a last instruction in said block of two or more program instructions is being processed to provide to said instruction fetching circuit said indication of said memory location of said instruction following said execute block instruction so that said instruction following said execute block instruction is fetched for execution immediately following said last instruction in said block of two or more program instructions.    
   
   
       2 . The data processing apparatus as claimed in  claim 1 , wherein 
 said execute block instruction logic is operable in response to said execute block instruction to store an indication of said memory location specified by said location field within said execute block instruction, said execute block instruction logic being further operable when it is determined that said execute block instruction is being processed to provide to said instruction fetching circuit said indication of said memory location specified by said location field within said execute block instruction so that instructions in said block of two or more program instructions are fetched for execution immediately following said execute block instruction.    
   
   
       3 . The data processing apparatus as claimed in  claim 2 , wherein 
 said execute block instruction logic comprises storage operable to store said indication of said memory location of said instruction following said execute block instruction, which indication being associated as a target memory location with said last instruction in said block of two or more program instructions.    
   
   
       4 . The data processing apparatus as claimed in  claim 3 , wherein 
 said storage is further operable to store said indication of said memory location specified by said location field within said execute block instruction, which indication being associated as a target memory location with said execute block instruction.    
   
   
       5 . The data processing apparatus as claimed in  claim 3 , wherein 
 said storage contains a number of entries, each entry having a field for storing an indication of said memory location of an instruction and an associated field for storing an indication of a corresponding target memory location.    
   
   
       6 . The data processing apparatus as claimed in  claim 3 , wherein 
 said storage comprises a return stack operable to store said indication of said memory location of said instruction following said execute block instruction, which indication being associated as said target memory location with said last instruction in said block of two or more program instructions.    
   
   
       7 . The data processing apparatus as claimed in  claim 6 , wherein 
 said execute block instruction logic is further operable to push said indication of said memory location of said instruction following said execute block instruction onto said return stack in response to said execute block instruction.    
   
   
       8 . The data processing apparatus as claimed in  claim 7 , wherein 
 said execute block instruction logic is operable, in the event that it is determined that said last instruction in said block of two or more program instructions is being processed and said storage provides a target memory location associated with said last instruction in said block of two or more program instructions, to disregard said target memory location associated with said last instruction in said block of two or more program instructions and instead to pop said return stack and to provide to said instruction fetching circuit said indication of said memory location popped from said return stack.    
   
   
       9 . The data processing apparatus as claimed in  claim 7 , wherein 
 said execute block instruction logic comprises interrupt handling logic which, in the event of an interrupt, stores an indication of said memory location of said execute block instruction and an indication of which instruction in said block of two or more program instructions is being executed when said interrupt occurs to enable upon completion of handling of said interrupt restarting execution of said block of two or more program instructions at a program instruction within said block of two or more instructions indicated by said indication of said memory location of said execute block instruction and said indication of which instruction in said block of two or more program instructions is being executed.    
   
   
       10 . The data processing apparatus as claimed in  claim 9 , wherein 
 said interrupt handling logic prevents the pushing of said indication of said memory location of said instruction following said execute block instruction onto said return stack in response to said execute block instruction being processed following said interrupt.    
   
   
       11 . The data processing apparatus as claimed in  claim 4 , wherein 
 said execute block instruction logic comprises prediction logic operable to receive an indication of each instruction being fetched by said instruction fetching circuit and to determine whether that instruction has associated therewith a target memory address and, if so, to provide said target memory address to said instruction fetching circuit so that the instruction at that memory address is fetched for execution immediately following that instruction.    
   
   
       12 . The data processing apparatus as claimed in  claim 11 , further comprising 
 prediction prevention logic operable to prevent prediction logic from providing said target memory address to said instruction fetching circuit for non-branch encoded instructions, said execute block instruction logic comprising prediction prevention override logic operable to inhibit operation of said prediction prevention logic when said last instruction in said block of two or more program instructions is being processed.    
   
   
       13 . The data processing apparatus as claimed in  claim 1 , wherein 
 said execute block instruction logic comprises a counter operable to provide an indication of which instruction in said block of two or more program instructions is being processed.    
   
   
       14 . The data processing apparatus as claimed in  claim 1 , wherein 
 said execute block instruction logic is operable when it is determined that a last instruction in said block of two or more program instructions is being processed to provide to said instruction fetching circuit said indication of said memory location of said instruction immediately following said execute block instruction.    
   
   
       15 . A method of processing data, comprising 
 fetching a sequence of program instructions from a sequence of memory locations with an instruction fetching circuit;    controlling data processing operations specified by said program instructions with an instruction decoder responsive to program instructions within said sequence of program instructions fetched by said instruction fetching circuit; and    executing said data processing operations with an execution circuit under control of said instruction decoder, wherein    said instruction decoder is responsive to an execute block instruction within said sequence of program instructions to trigger fetching of a block of two or more program instructions by said instruction fetching circuit and execution of said block of two or more program instructions by said execution circuit, said block of two or more instructions containing a number of program instructions specified by a block length field within said executed block instruction and being stored at a memory location specified by a location field within said execute block instruction, said method further comprising,    storing, in response to said execute block instruction, an indication of a memory location of an instruction following said execute block instruction and determining which instruction in said block of two or more program instructions is being processed, and    when it is determined that a last instruction in said block of two or more program instructions is being processed, providing to said instruction fetching circuit said indication of said memory location of said instruction following said execute block instruction so that said instruction following said execute block instruction is fetched for execution immediately following said last instruction in said block of two or more program instructions.    
   
   
       16 . The method as claimed in  claim 15 , comprising: 
 storing, in response to said execute block instruction, an indication of said memory location specified by said location field within said execute block instruction and when it is determined that said execute block instruction is being processed to provide to said instruction fetching circuit said indication of said memory location specified by said location field within said execute block instruction so that instructions in said block of two or more program instructions are fetched for execution immediately following said execute block instruction.    
   
   
       17 . The method as claimed in  claim 16 , comprising 
 providing storage operable to store said indication of said memory location of said instruction following said execute block instruction, which indication being associated as a target memory location with said last instruction in said block of two or more program instructions.    
   
   
       18 . The method as claimed in  claim 17 , comprising 
 providing storage operable to store said indication of said memory location specified by said location field within said execute block instruction, which indication being associated as a target memory location with said execute block instruction.    
   
   
       19 . The method as claimed in  claim 17 , wherein 
 said storage contains a number of entries, each entry having a field for storing an indication of said memory location of an instruction and an associated field for storing an indication of a corresponding target memory location.    
   
   
       20 . The method as claimed in  claim 17 , wherein 
 said storage comprises a return stack operable to store said indication of said memory location of said instruction following said execute block instruction, which indication being associated as said target memory location with said last instruction in said block of two or more program instructions.    
   
   
       21 . The method as claimed in  claim 20 , comprising 
 pushing said indication of said memory location of said instruction following said execute block instruction onto said return stack in response to said execute block instruction.    
   
   
       22 . The method as claimed in  claim 21 , comprising 
 disregarding, in the event that it is determined that said last instruction in said block of two or more program instructions is being processed and said storage provides a target memory location associated with said last instruction in said block of two or more program instructions, said target memory location associated with said last instruction in said block of two or more program instructions and instead to pop said return stack and to provide to said instruction fetching circuit said indication of said memory location popped from said return stack.    
   
   
       23 . The method as claimed in  claim 21 , comprising 
 storing, in the event of an interrupt, an indication of said memory location of said execute block instruction and an indication of which instruction in said block of two or more program instructions is being executed when said interrupt occurs to enable upon completion of handling of said interrupt restarting execution of said block of two or more program instructions at a program instruction within said block of two or more instructions indicated by said indication of said memory location of said execute block instruction and said indication of which instruction in said block of two or more program instructions is being executed.    
   
   
       24 . The method as claimed in  claim 23 , comprising 
 preventing the pushing of said indication of said memory location of said instruction following said execute block instruction onto said return stack in response to said execute block instruction being processed following said interrupt.    
   
   
       25 . The method as claimed in  claim 18 , comprising 
 receiving an indication of each instruction being fetched by said instruction fetching circuit and determining whether that instruction has associated therewith a target memory address and, if so, providing said target memory address to said instruction fetching circuit so that the instruction at that memory address is fetched for execution immediately following that instruction.    
   
   
       26 . The method as claimed in  claim 25 , comprising 
 inhibiting the operation of prediction prevention logic which prevents said target memory address from being provided to said instruction fetching circuit for non-branch encoded instructions when said last instruction in said block of two or more program instructions is being processed.    
   
   
       27 . The method as claimed in  claim 15 , comprising 
 providing an indication of which instruction in said block of two or more program instructions is being processed.    
   
   
       28 . The method as claimed in  claim 15 , comprising 
 providing, when it is determined that a last instruction in said block of two or more program instructions is being processed, said instruction fetching circuit with said indication of said memory location of said instruction immediately following said execute block instruction.