Method and resulting structure for manufacturing semiconductor substrates

Abstract

A semiconductor wafer composite is used as a basis for fabricating semiconductor chips, especially compound semiconductor devices. The semiconductor wafer composite advantageously comprises a metallic substrate 210 and multiple semiconductor tiles 220 bonded to the surface of the metallic substrate 210. The semiconductor wafer composite is effectively used as a single large semiconductor wafer for volume fabrication, and can be used to fabricate semiconductor devices in a similar manner.

1 . A bonded semiconductor wafer composite for fabricating semiconductor devices, the bonded semiconductor wafer comprising: 
 a metal support substrate having a first diameter, the metal support substrate including an upper surface, the upper surface being substantially planar, the metal support structure being characterized by a first coefficient of thermal expansion parameter;    a plurality of trapezoidal shaped tiles comprising a compound semiconductor material, the plurality of trapezoidal shaped tiles being bonded onto the upper surface of the metal support substrate, each of the trapezoidal shaped tiles including at least one edge, the one edge being aligned with an edge of a different trapezoidal shaped tile, each of the plurality of trapezoidal shaped tiles being characterized by a second coefficient of thermal expansion parameter;    a eutectic bonding material coupled between each of the trapezoidal shaped tiles and a portion of the upper surface of the metal support substrate, the eutectic bonding material providing a continuous mechanical and electrical contact between the portion of the upper surface and the trapezoidal shaped tile;    wherein the first coefficient of thermal expansion parameter is within a predetermined amount of the second coefficient of thermal expansion parameter, the predetermined amount being selected to reduce a possibility of breakage of any portion of any trapezoidal shaped tile bonded to the portion of the upper surface of the metal substrate from a thermal influence; and    wherein each of the trapezoidal shaped tiles being derived from a compound semiconductor substrate of a second diameter, the second diameter being less than the first diameter associated with the metal substrate; each of the trapezoidal shaped tiles comprising a predetermined thickness.    
     
     
         2 . A semiconductor wafer composite for fabricating a semiconductor device, the semiconductor wafer composite comprising: 
 a metallic substrate; and    at least one semiconductor tile bonded to the metallic substrate.    
     
     
         3 . The semiconductor wafer composite as claimed in  claim 2 , wherein the at least one semiconductor tile is sequentially (i) cut to a predetermined shape, (ii) thinned, and (iii) bonded to the metallic substrate.  
     
     
         4 . The semiconductor wafer composite as claimed in  claim 2 , wherein the at least one semiconductor tile is sequentially (i) thinned, (ii) cut to a predetermined shape, and (iii) bonded to the metallic substrate.  
     
     
         5 . The semiconductor wafer composite as claimed in  claim 2 , wherein the at least one semiconductor tile is sequentially (i) cut to a predetermined shape, (ii) bonded to the metallic substrate, and (iii) thinned.  
     
     
         6 - 7 . (canceled)  
     
     
         8 . The semiconductor wafer composite as claimed in  claim 2 , wherein the semiconductor wafer composite is diced to form individual integrated circuits having metallic substrates.  
     
     
         9 . The semiconductor wafer composite as claimed in  claim 2 , wherein the metallic substrate comprises a metallic base layer, and a bonding layer to which the at least one semiconductor tile is bonded.  
     
     
         10 . (canceled)  
     
     
         11 . The semiconductor wafer composite as claimed in  claim 2 , wherein the at least one semiconductor tile comprises a compound semiconductor.  
     
     
         12 - 13 . (canceled)  
     
     
         14 . The semiconductor wafer composite as claimed in  claim 9 , wherein the bonding layer is predominantly formed of two or more metals that form a eutectic alloy when heated.  
     
     
         15 . (canceled)  
     
     
         16 . The semiconductor wafer composite as claimed in  claim 2 , wherein the metallic substrate and the at least one semiconductor tile have respective coefficients of thermal expansion that are substantially similar values.  
     
     
         17 . The semiconductor wafer composite as claimed in  claim 2 , wherein the at least one semiconductor tile has a substantially rectangular or square shape.  
     
     
         18 - 33 . (canceled)  
     
     
         34 . A semiconductor wafer composite for fabricating a semiconductor device, the semiconductor wafer composite manufactured by a process comprising the steps of: 
 providing a metallic substrate; and    bonding at least one semiconductor tile to the metallic substrate.    
     
     
         35 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) thinning the at least one semiconductor tile, and (iii) bonding the at least one semiconductor tile to the metallic substrate.  
     
     
         36 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises sequentially (i) thinning the at least one semiconductor tile, (ii) cutting the at least one semiconductor tile to a predetermined shape, and (iii) bonding the at least one semiconductor tile to the metallic substrate.  
     
     
         37 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises sequentially (i) cutting the at least one semiconductor tile to a predetermined shape, (ii) bonding the at least one semiconductor tile to the metallic substrate, and (iii) thinning the at least one semiconductor tile.  
     
     
         38 - 39 . (canceled)  
     
     
         40 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises dicing the semiconductor wafer composite to form individual integrated circuits having metallic substrates.  
     
     
         41 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises forming the metallic substrate from a metallic base layer, and a bonding layer to which the at least one semiconductor tile is bonded.  
     
     
         42 . (canceled)  
     
     
         43 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises forming the at least one semiconductor tile with a working layer predominantly of a compound semiconductor.  
     
     
         44 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises forming the at least one semiconductor tile with a complementary bonding layer suitable for adhering the at least one semiconductor tile to the metallic substrate.  
     
     
         45 . The semiconductor wafer composite as claimed in  claim 44 , wherein the process further comprises forming the complementary bonding layer predominantly of one or more metals, one of which is a noble metal.  
     
     
         46 . The semiconductor wafer composite as claimed in  claim 41 , wherein the process further comprises forming the bonding layer predominantly of two or more metals that form a eutectic-alloy when heated.  
     
     
         47 . (canceled)  
     
     
         48 . The semiconductor wafer composite as claimed in  claim 34 , wherein the process further comprises matching respective coefficients of thermal expansion of the at least one semiconductor tile and the metallic substrate to substantially similar values.  
     
     
         49 . The method as claimed in  claim 34 , wherein the process further comprises cutting a semiconductor wafer to a substantially rectangular or square shape to form the at least one semiconductor tile.  
     
     
         50 . (canceled)  
     
     
         51 . A packaged compound semiconductor integrated circuit device comprising: 
 a compound semiconductor substrate comprising a backside surface;    a metal substrate bonded to the backside surface, the metal substrate providing mechanical support for the compound semiconductor substrate before being packaged; and    a support substrate coupled to the metal substrate for packaging.