US2005255641A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: MITSUBISHI ELECTRIC CORPPriority: Mar 1, 2002Filed: Jul 25, 2005Published: Nov 17, 2005
Est. expiryMar 1, 2022(expired)· nominal 20-yr term from priority
H10P 10/00H10D 84/0151H10D 30/0212H10D 84/0137H10D 84/038H10D 84/013H10D 30/0227H10B 99/00
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Claims

Abstract

It is an object to suppress a change in a characteristic of a semiconductor device with a removal of a hard mask while making the most of an advantage of a gate electrode formed by using the hard mask. A gate electrode ( 3 ) is formed by etching using a hard mask as a mask and the hard mask remains on an upper surface of the gate electrode ( 3 ) at a subsequent step. In the meantime, the upper surface of the gate electrode ( 3 ) can be therefore prevented from being unnecessarily etched. The hard mask is removed after ion implantation for forming a source-drain region. Consequently, the influence of the removal of the hard mask on a characteristic of a semiconductor device can be suppressed. In that case, moreover, a surface of a side wall ( 4 ) is also etched by a thickness of (d) so that an exposure width of an upper surface of the source-drain region is increased. After the removal of the hard mask, it is easy to salicide the gate electrode ( 3 ) and to form a contact on the gate electrode ( 3 ).

Claims

exact text as granted — not AI-modified
1 - 11 . (canceled)  
   
   
       12 . A semiconductor device comprising: 
 a first gate electrode formed on a semiconductor substrate;    a side wall formed on a side surface of said first gate electrode; and    a source-drain region formed in said semiconductor substrate and having a low impurity concentration region provided so as to sandwich said gate electrode and a high impurity concentration region provided outside said low impurity concentration region so as to sandwich said gate electrode;    wherein a width of said side wall is smaller than a space between said first gate electrode and said high impurity concentration region, and    a contact is formed on an upper surface of said source-drain region.    
   
   
       13 . The semiconductor device according to  claim 12 , further comprising: 
 a second gate electrode formed on said semiconductor substrate; and    a hard mask formed on an upper surface of said second gate electrode.    
   
   
       14 . (canceled)

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