US2005251352A1PendingUtilityA1

Measurement interface optimized for both differential and single-ended inputs

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Individually held — no corporate assignee on recordPriority: Oct 30, 2003Filed: Jun 23, 2005Published: Nov 10, 2005
Est. expiryOct 30, 2023(expired)· nominal 20-yr term from priority
Inventors:Michael Mctigue
H03K 5/2481H03K 5/249H03F 3/45968H03F 3/45475
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Claims

Abstract

Offset adjustments for both differential and single-ended measurements are accomplished in the same probe or system. Different variable offsets are provided for the positive and negative inputs of a differential amplifier, and a variable offset adjustment is provided to remove differential amplifier output offset. Common mode and reduced dynamic range problems for both differential and single-ended measurements are eliminated. All or desired portions of required functions may be implemented using discrete or DSP approaches.

Claims

exact text as granted — not AI-modified
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       16 . A method of optimizing single-ended and differential inputs received by the measurement interface, comprising: 
 selectively modifying offset from a first input;    selectively modifying offset from a second input;    generating the algebraic difference of the first and second inputs after offset has been selectively modified from said first and second inputs; and    adjusting a final output offset to nullify a differential amplifier offset or to establish a desired DC output component on an output of the measurement interface.    
   
   
       17 . The method of  claim 16 , further comprising: 
 enabling a first switch to allow variability of a first final offset;    disabling a second switch to force a zero value for a second final offset;    disabling a third switch to force a third final offset to zero; and    adjusting a first offset voltage to produce zero static DC level of the output.    
   
   
       18 . The method of  claim 16 , further comprising: 
 enabling a first switch to allow variability of a first final offset;    disabling a second switch to force zero for a second final offset;    enabling a third switch to allow variability of a third final offset;    adjusting a first offset voltage for zero offset at a first differential amplifier input; and    adjusting a third offset voltage to null the differential amplifier offset or to establish an output DC offset of the output.    
   
   
       19 . The method of  claim 16 , further comprising: 
 enabling a first switch to allow variability of a first final offset;    enabling a second switch to allow variability of a second final offset;    disabling a third switch to force a third final offset to zero;    adjusting a first offset voltage for zero offset at a first differential amplifier input; and    adjusting a second offset voltage for zero offset at a second differential amplifier input.    
   
   
       20 . The method of  claim 16 , further comprising: 
 enabling a first switch to allow variability of a first final offset;    enabling a second switch to allow variability of a second final offset;    enabling a third switch to allow variability of a third final offset;    adjusting a first offset voltage for zero offset of a first differential amplifier input;    adjusting a second offset voltage for zero offset of a second differential amplifier input; and    adjusting a third offset voltage to null the differential amplifier offset or to establish an output DC offset of the output.    
   
   
       21 . The method of  claim 16 , further comprising: 
 disabling a first switch to force a first final offset to zero;    enabling a second switch to allow variability of a second final offset;    enabling a third switch to allow variability of a third final offset;    adjusting a second offset voltage for zero offset at a differential amplifier input; and    adjusting a third offset voltage to null a differential amplifier offset or to establish an output DC offset of the output.    
   
   
       22 . The method of  claim 16 , further comprising: 
 disabling a first switch to force a first final offset to zero;    disabling a second switch to force a second final offset to zero;    enabling a third switch to allow variability of a third final offset; and    adjusting a third offset voltage to null the differential amplifier offset or to establish an output DC offset of the output.    
   
   
       23 . The method of  claim 16 , further comprising: 
 disabling a first switch to force a first final offset to zero;    disabling a second switch to force a second final offset to zero; and    disabling a third switch to force a third final offset to zero; and    performing measurements without signal offset modifications by the measurement interface.    
   
   
       24 . The method of  claim 16 , further comprising: 
 disabling a first switch to force a first final offset to zero;    enabling a second switch to allow variability of a second final offset;    disabling a third switch to force a third final offset to zero; and    adjusting a second offset voltage for zero offset of a differential amplifier input.    
   
   
       25 . An apparatus operable to receive and operate on first and second inputs of a measurement interface, comprising: 
 first means for selectively modifying offset from the first input;    second means for selectively modifying offset from the second input;    means for generating the algebraic difference of first and second inputs after offset has been selectively removed from each; and    third means for selectively modifying a final output offset of an output.    
   
   
       26 . A measurement interface capable of optimizing single-ended and differential inputs received by the measurement interface, comprising: 
 a first summation element operable to selectively modify offset from a first input and generate a first summation element output;    a second summation element operable to selectively modify offset from a second input and generate a second summation element output; and    a difference element that receives the first and second summation element outputs and generates the difference between said first and second summation element outputs at an output of the difference element.    
   
   
       27 . The interface of  claim 26 , wherein the difference element is a differential amplifier.  
   
   
       28 . The interface of  claim 26 , further comprising: 
 a third summation element operable to selectively modify offset from the output.

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