Method and System For A Variable Frequency SDRAM Controller

Abstract

A method for providing a variable frequency clock for a SDRAM. First, receiving a clock with a fixed frequency and a plurality of signals, wherein each the signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals. Second, extracting a plurality of proper positions from the signals, wherein each low level of each the signal corresponds to a proper position. Third, amending the frequency of the clock such that each the proper position corresponds to a rising edge of the clock.

1 . A method for providing a variable frequency clock for a SDRAM, comprising: 
 receiving a clock with a fixed frequency and a plurality of signals, wherein each said signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals;    extracting a plurality of proper positions from said signals, wherein each low level of each said signal corresponds to a proper position; and    amending the frequency of said clock such that each said proper position corresponds to a rising edge of said clock.    
   
   
       2 . The method of  claim 1 , wherein each said proper position is located at the center of corresponding said low level.  
   
   
       3 . The method of  claim 1 , wherein each said proper position is located at a safety region around the center of corresponding said low level.  
   
   
       4 . The method of  claim 1 , wherein each said proper position is located at a safety region inside corresponding said low level.  
   
   
       5 . The method of  claim 1 , wherein the step of amending the frequency of said clock is performed by the following steps chosen from the group consisting of the following: multiply frequency, divide frequency, mix said clock with at least one higher frequency clock, using doubled edges of the clock, using and the combination thereof.  
   
   
       6 . A system for providing a variable frequency clock for a SDRAM, comprising: 
 a receiver for receiving a clock with a fixed frequency and a plurality of signals, wherein each said signal is an interlace combination of a plurality of high level signals and a plurality of low levels signals;    an extractor for extracting a plurality of proper positions from said signals, wherein each low level of each said signal corresponds to a proper position; and    an amender for amending the frequency of said clock such that each said proper position corresponds to a rising edge of said clock.    
   
   
       7 . The system of  claim 1 , wherein said extractor locates each said proper position at the center of corresponding said low level.  
   
   
       8 . The system of  claim 1 , wherein said extractor locates each said proper position at a safety region around the center of corresponding said low level.  
   
   
       9 . The system of  claim 1 , wherein said extractor locates each said proper position at a safety region inside corresponding said low level.  
   
   
       10 . The system of  claim 1 , wherein said amender is a combination of the parts chosen from the group consisting of the following: frequency multiplier, frequency divider, mixer that receive said clock and at least one higher frequency clock, and the combination thereof.