Shallow trench isolation void detecting method and structure for the same

Abstract

Disclosed is a. method for detecting STI void of a semiconductor wafer. The method of the present invention comprises steps of assigning a detecting area in a predetermined region of the wafer; forming active areas and gate strips crossing the active areas by the process synchronized with that for other regions of the wafer. Dielectric material is filled between the active areas. The adjacent portion between the active areas reaches a predetermined length at least. The electrical value of the gate strips is measured to determine whether there is any void in the dielectric filled between the active areas, thereby to derive whether there is any void generated in the STI between the active areas of the other regions of the wafer.

1 . A method for detecting STI void of semiconductor wafer, comprising steps of 
 assigning a test region in a predetermined region of the wafer;    forming active areas, trenches between the active areas and gate lines intersecting with tthe active areas, said trenches being filled with dielectric, and said active areas having their adjacent portion reaching at least a predetermined length; and    measuring the electric values of said gate lines to determine whether there is a void formed in the trench.    
   
   
       2 . The method as claimed in  claim 1 , wherein said active areas in the testing region are formed as parallel strips.  
   
   
       3 . The method as claimed in  claim 1 , wherein odd ones of said gate lines are connected together, while even ones of the gate lines are connected together, so as to form a dual-comb structure.  
   
   
       4 . The method as claimed in  claim 3 , wherein said measuring step is to measure the potentials of the comb structure of the odd gate lines and the comb structure of the even gate lines.  
   
   
       5 . The method as claimed in  claim 1 , wherein the testing region is formed on a predetermined cutting line of the wafer.  
   
   
       6 . A testing region structure for STI void detection of semiconductor wafer, said test region structure being formed on the wafer by a process synchronous with other portions of the wafer, said structure comprising: 
 a plurality of active areas, the adjacent portion between two active areas reaching at least a predetermined length;    a plurality of trenches formed between the active areas and being filled with dielectric; and    a plurality of gate lines intersecting with said active areas.    
   
   
       7 . The structure as claimed in  claim 6 , wherein said active areas in the testing region are formed as parallel strips.  
   
   
       8 . The structure as claimed in  claim 6 , wherein the odd ones of the gate lines are connected together, while the even ones of the gate lines are connected together, so as to constitute a dual-comb structure.  
   
   
       9 . The structure as claimed in  claim 6 , wherein the testing region structure is formed on a predetermined cutting line of the wafer.