Bus structure, database and method of designing interface

Abstract

With respect to each application, libraries, corresponding to operation models, for describing operations respectively attained by employing a Neumann CPU (bus structure), a Harvard CPU (bus structure) and a direction separate type CPU (bus structure) are registered. In a performance table of each library, the performance index of the library is expressed as a function of parameters of throughput, a bus width, instruction quantity and memory size. Also, a portion of the operation realized by using software and a portion realized by using hardware are registered. Through operation simulation conducted with each application successively replaced with each of the libraries, the performance of a semiconductor integrated circuit can be evaluated, so as to synthesize an optimal interface.

1 . A bus structure for connection between a control circuit and plural circuits to be controlled in a semiconductor integrated circuit, comprising: 
 an address bus divided into an upstream bus and a downstream bus; and    a data bus divided into an upstream bus and a downstream bus.    
   
   
       2 . The bus structure of  claim 1 , 
 wherein said data bus is divided with respect to each of said plural circuits to be controlled and each divided portion of said data bus is further divided into an upstream bus and a downstream bus.    
   
   
       3 . A database for use in design of a semiconductor integrated circuit comprising: 
 a table including description of kinds of bus structures for connection between a control function part and plural applications.    
   
   
       4 . The database of  claim 3 , 
 wherein said table includes a performance table describing a performance index for evaluating performance attained by an operation model of each of said applications.    
   
   
       5 . The database of  claim 4 , 
 wherein said performance table includes, as said performance index, at least one of parameters of throughput, a bus width, instruction quantity and memory size.    
   
   
       6 . The database of  claim 3 , 
 wherein said performance table includes, as the description of kinds of bus structures, description of a separate type bus structure having an address bus divided into an upstream bus and a downstream bus and a data bus divided into an upstream bus and a downstream bus.    
   
   
       7 - 19 . (canceled)