Error handling system in a redundant processor

Abstract

In a redundant-processor computing device, an error handling method comprises detecting equivalent disparity among processor elements of the computing device operating and responding to the detected equivalent disparity by evaluating secondary considerations of processor fidelity.

1 . A control apparatus for usage in a redundant-processor computing device including a plurality of processor elements, the control apparatus comprising: 
 a control element that detects equivalent disparity among the processor elements and responds by evaluating secondary considerations of processor fidelity.    
   
   
       2 . The apparatus according to  claim 1  further comprising: 
 a control element that determines whether evaluation of the secondary considerations is insufficient to resolve the equivalent disparity among the processor elements and, if so, terminates operations of the computing device.    
   
   
       3 . The apparatus according to  claim 2  further comprising: 
 a control element that interjects a delay between equivalent disparity detection and the evaluation of secondary considerations of processor fidelity.    
   
   
       4 . The apparatus according to  claim 1  further comprising: 
 a control element that determines whether the evaluation of the secondary considerations is sufficient to resolve the equivalent disparity among the processor elements and, if so, completes an operation according to the resolution.    
   
   
       5 . The apparatus according to  claim 1  further comprising: 
 a control element that evaluates the secondary conditions of processor fidelity and sets a probation vector according to the evaluation.    
   
   
       6 . The apparatus according to  claim 1  further comprising: 
 a processor element that evaluates the secondary conditions of processor fidelity and sets a probation vector according to the evaluation.    
   
   
       7 . The apparatus according to  claim 1  wherein an equivalent disparity condition comprises one or more of conditions including: 
 a condition of a first processor element performing a programmed input/output (PIO) action while a second processor element does not;    a condition of a first processor element performing a PIO read while a second processor element performs a PIO write;    a condition of a first processor and a second processor reading different addresses;    a condition of a first processor and a second processor writing different addresses; and    a miscompare on voted data whereby data supplied by two processor elements does not match on a programmed input/output (PIO) action or a direct memory access (DMA) action.    
   
   
       8 . An error handling method in a redundant-processor computing device comprising: 
 detecting equivalent disparity among processor elements of the computing device; and    responding to the detected equivalent disparity by evaluating secondary considerations of processor fidelity.    
   
   
       9 . The method according to  claim 8  further comprising: 
 determining whether the evaluation of the secondary considerations is insufficient to resolve the equivalent disparity among the processor elements; and    if so, terminating operations of the computing device.    
   
   
       10 . The method according to  claim 9  further comprising: 
 inserting a delay between equivalent disparity detection and termination of computer device operation.    
   
   
       11 . The method according to  claim 8  further comprising: 
 determining whether evaluation of the secondary considerations is sufficient to resolve the equivalent disparity among the processor elements; and    if so, completing an operation according to the resolution.    
   
   
       12 . The method according to  claim 8  further comprising: 
 evaluating the secondary conditions of processor fidelity; and    setting a probation vector according to the evaluation.    
   
   
       13 . The method according to  claim 8  wherein an equivalent disparity condition one or more of conditions including: 
 a condition of a first processor element performing a programmed input/output (PIO) action while a second processor element does not;    a condition of a first processor element performing a PIO read while a second processor element performs a PIO write;    a condition of a first processor and a second processor reading different addresses;    a condition of a first processor and a second processor writing different addresses; and    a miscompare on voted data whereby data supplied by two processor elements does not match on a programmed input/output (PIO) action or a direct memory access (DMA) action.    
   
   
       14 . A computing system comprising: 
 a plurality of processor elements configured in a redundant-processor arrangement;    a voter coupled to the plurality of processor elements that compares actions taken by the processor elements and determines disparity in the actions; and    a control element coupled to the processor elements and the voter that detects equivalent disparity among the processor elements and responds by evaluating secondary considerations of processor fidelity.    
   
   
       15 . The system according to  claim 14  further comprising: 
 a two-processor element configuration; and    a programmed input/output (PIO) interface coupled to the voter whereby an action disparity that is detectable by the control element is a PIO timeout with one processor element performing a PIO action and one processor element not performing the PIO action.    
   
   
       16 . The system according to  claim 14  further comprising: 
 a two-processor element configuration; and    a programmed input/output (PIO) interface and a direct memory access (DMA) interface coupled to the voter whereby an action disparity that is detectable by the control element is a miscompare on voted data with non-matching data supplied by two processor elements either on a PIO action or a DMA action.    
   
   
       17 . The system according to  claim 14  further comprising: 
 a probation vector coupled to the voter and coupled to the processor elements and having a signal allocated to each of the processor elements; and    a control element that evaluates the secondary conditions of processor fidelity and sets the probation vector according to the secondary considerations of processor fidelity.    
   
   
       18 . The system according to  claim 14  further comprising: 
 a control element that determines whether evaluation of the secondary considerations is insufficient to resolve the disparity among the processor elements and, if so, terminates computing device operations.    
   
   
       19 . The system according to  claim 18  further comprising: 
 a control element that interjects a delay between equivalent disparity detection and evaluation of secondary considerations of processor fidelity.    
   
   
       20 . A computing system comprising: 
 a plurality of processor elements configured in a redundant-processor arrangement;    a probation vector coupled to the processor elements and having a signal allocated to each of the processor elements; and    a logic that evaluates processor fidelity and sets the probation vector according to the evaluation.    
   
   
       21 . The system according to  claim 20  further comprising: 
 a control element that evaluates processor fidelity and sets a probation vector according to the evaluation.    
   
   
       22 . The system according to  claim 20  further comprising: 
 a processor element that evaluates processor fidelity and sets a probation vector according to the evaluation.    
   
   
       23 . The system according to  claim 20  further comprising: 
 a voter coupled to the plurality of processor elements that compares actions taken by the processor elements and determines disparity in the actions; and    a control-element that responds-to disparity among the processor elements based on the probation vector.    
   
   
       24 . The system according to  claim 23  further comprising: 
 a control element that interjects a delay between disparity detection and computer device operation termination.    
   
   
       25 . The system according to  claim 20  further comprising: 
 a control element that determines whether evaluation of processor fidelity is insufficient to resolve the disparity among the processor elements and, if so, terminates computing system operations.    
   
   
       26 . The system according to  claim 20  wherein for a two-processor system a disparity condition comprises one or more conditions selected from a group consisting of: 
 a condition of a first processor element performing a programmed input/output (PIO) action while a second processor element does not;    a condition of a first processor element performing a PIO read while a second processor element performs a PIO write;    a condition of a first processor and a second processor reading different addresses;    a condition of a first processor and a second processor writing different addresses; and    a miscompare on voted data whereby data supplied by two processor elements does not match on a programmed input/output (PIO) action or a direct memory access (DMA) action.    
   
   
       27 . A computing system comprising: 
 a plurality of processor elements configured in a redundant-processor arrangement; and    control logic coupled to the processor element plurality that mutually compares actions taken by ones of the processor elements and determines equivalent disparity in the actions, and waits a selected delay after equivalent disparity detection before initiating an action responsive to the disparity condition.    
   
   
       28 . The computing system according to  claim 27  further comprising: 
 control logic that responds after the delay according to evaluation of secondary considerations of processor fidelity.    
   
   
       29 . The computing system according to  claim 27  wherein: 
 the selected delay has a duration sufficient to enable near-simultaneous arrival of information for usage in resolving the disparity condition.