Semiconductor device, semiconductor system, and digital delay circuit

Abstract

Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

1 . A delay circuit, comprising: 
 a variable delay circuit, including a plurality of delay units connected in cascade, for delaying a timing signal for a delay time to output a delayed timing signal; and    a delay control circuit, outputting control signals to select one of the plurality of delay units, for controlling the delay time of the variable delay circuit,    wherein each delay unit comprises: 
 a first input node receiving the timing signal;  
 a second input node receiving an output signal of the preceding stage of the delay unit;  
 a control node receiving one of the control signals;  
 an output node; and  
 a logic gate portion for coupling one of the timing signal and the output signal of the preceding stage to the output node in response to the control signal.  
   
   
   
       2 . The delay circuit according to  claim 1 , wherein the timing signal is a clock signal.  
   
   
       3 . The delay circuit according to  claim 1 , wherein the delay circuit is included in a DLL circuit of a semiconductor device that operates synchronously with a clock signal.  
   
   
       4 . The delay circuit according to  claim 1 , wherein the number of the delay units through which the timing signal propagates is selected by the control signals.  
   
   
       5 . The delay circuit according to  claim 1 , wherein the delay control circuit comprises a plurality of latch circuits, and each latch circuit generates one of the control signals.  
   
   
       6 . The delay circuit according to  claim 1 , wherein the timing signal couples to the plurality of delay units in parallel.  
   
   
       7 . The delay circuit according to  claim 1 , wherein said each delay unit includes a delay element.  
   
   
       8 . The delay circuit according to  claim 7 , wherein the delay element is an inverter circuit.  
   
   
       9 . The delay circuit according to  claim 1 , wherein the logic gate includes a NAND gate circuit.  
   
   
       10 . The delay circuit according to  claim 1 , wherein the delay control circuit comprises an up/down counter.