Improved metal wiring pattern for memory devices

Abstract

A memory integrated circuit having three layers of metallic traces disposed over a substrate assembly including various active devices. The traces are arranged to include I/O traces that are continuous in the third layer across spans of 4 or 8 memory blocks of an array, and that are interspersed on the third layer with non-I/O lines adapted to reduce interference between I/O lines. Column select lines, orthogonal to I/O lines and disposed in the third layer of metallic traces, except in the vicinity of I/O lines, are provided in a linear configuration and shielded from parallel digit lines in the first layer of traces by traces of the intervening second layer of traces. Global bleeder lines disposed in the third layer of traces are adapted to apply a standby voltage to a plurality of sense amplifiers. Other features of the invention include two layer power and ground bus traces, and row decoder and phase driver circuits disposed in throat and gap cell regions respectively.

1 - 3 . (canceled)  
   
   
       4 . An integrated circuit memory device comprising: 
 a substrate assembly, said substrate assembly including a plurality of memory arrays, said memory arrays each including a plurality of memory blocks; and    first, second, and third layers of metalization, wherein one of said layers includes at least one I/O line that is continuous within said one layer over a span of two or more memory blocks.    
   
   
       5 . A device, as in  claim 4 , wherein a memory array includes at least four memory blocks, and wherein said at least one I/O line is continuous within said one layer over a span of said at least four memory blocks.  
   
   
       6 . A device, as in  claim 4 , wherein a memory array includes at least eight memory blocks, and wherein said at least one I/O line is continuous within said one layer over a span of said at least eight memory blocks.  
   
   
       7 . An integrated circuit memory device comprising: 
 a substrate assembly including a memory array;    said memory array including a plurality of memory blocks, at least eight of said memory blocks being arranged in spaced relation to one another in a first direction relative to said substrate assembly;    a sense amplifier stripe having a longitudinal axis oriented substantially parallel to said first direction;    first, second, and third layers of metallic traces disposed in substantially parallel spaced relation over said substrate assembly; and    an I/O trace disposed among said traces of one of said layers having a longitudinal axis oriented substantially parallel to said first direction.    
   
   
       8 . A device as in  claim 7  wherein said I/O trace spans at least four of said eight memory blocks.  
   
   
       9 . A device as in  claim 7  wherein said I/O trace spans at least eight of said memory blocks.  
   
   
       10 - 14 . (canceled)  
   
   
       15 . An integrated circuit memory device comprising: 
 a substrate assembly;    a layer of metallic traces including a local phase line trace;    a pair of wordline driver circuits, each of said circuits including one transistor of a pair of transistors formed within a common active region of said substrate assembly, said transistors sharing a common drain, said drain having a single connection to said local phase line trace.    
   
   
       16 . An integrated circuit memory device comprising: 
 a substrate assembly;    at least first, second, and third layers of metallic traces disposed in substantially parallel spaced relation over said substrate assembly;    a global bleeder circuit disposed within said substrate assembly and adapted to supply a standby voltage; and    a sense amplifier circuit disposed within said substrate assembly;    a global bleeder trace, at least a portion of which is disposed among said traces of said third layer of traces, operatively connected to both said bleeder circuit and said sense amplifier, and adapted to communicate said standby voltage from said bleeder circuit to said sense amplifier.    
   
   
       17 - 24 . (canceled)  
   
   
       25 . An integrated circuit memory device comprising: 
 two adjacent wordline driver circuits;    an active area having first and second transistors formed therein;    a portion of said active area including a doped region common to said two transistors;    one of said transistors being operatively connected to said first wordline driver circuit and the other of said transistors being operatively connected to said second wordline driver circuit.    
   
   
       26 . A device as in  claim 25  further comprising a local phase line including a point of connection operatively connected to said doped region.  
   
   
       27 . An integrated circuit memory device comprising: 
 a substrate assembly;    a layer of metalization over a substrate, said layer including at least one global bleeder line;    a bleeder device disposed within said substrate having an output operatively connected to said bleeder line; and    a plurality of sense amplifiers disposed within said substrate each amplifier of said plurality being operatively connected to said bleeder line.    
   
   
       28 . A device as in  claim 27  further comprising: 
 a plurality of additional layers of metal traces;    said plurality of layers disposed between said global bleeder line and said substrate assembly.    
   
   
       29 . A device as in  claim 27  further comprising: 
 a memory array block;    said block disposed within said substrate assembly;    one of said plurality of sense amplifiers being disposed on one side of said block, and another of said plurality of sense amplifiers being disposed on a second opposite side of said block.    
   
   
       30 . An integrated circuit memory device comprising: 
 a substrate assembly;    first and second memory arrays formed in said substrate assembly, said arrays disposed in spaced relation to one another and defining a throat therebetween;    a row decoder disposed in said substrate assembly within said throat;    a layer of metallic traces disposed in substantially parallel spaced relation over said substrate assembly; and    a global wordline trace disposed within said layer;    said global wordline trace being operatively connected to both said row driver and at least one of said arrays.    
   
   
       31 . A device as in  claim 30  further comprising: 
 at least one data read line and one data write line;    said lines being disposed adjacent said throat and within said layer of metallic traces.    
   
   
       32 - 45 . (canceled)