Flash memory device having a graded composition, high dielectric constant gate insulator

Abstract

A graded composition, high dielectric constant gate insulator is deposited between a substrate and floating gate in a flash memory cell transistor. If the composition of the gate insulator is closer to the high-k material near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the high-k material near the floating gate, the tunnel barrier can be lower at the floating gate.

1 . A flash memory transistor comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;    a graded composition, high dielectric constant gate insulator formed on top of the substrate and substantially between the plurality of source/drain regions, the gate insulator having a dielectric constant that is greater than 3.9;    a floating gate formed on top of the gate insulator;    an oxide insulator formed on top of the floating gate; and    a control gate formed on top of the oxide insulator.    
   
   
       2 . The transistor of  claim 1  wherein the gate insulator is formed by an evaporation technique.  
   
   
       3 . The transistor of  claim 1  wherein the gate insulator is formed by an atomic layer deposition technique.  
   
   
       4 . The transistor of  claim 1  wherein the graded composition of the gate insulator layer is a film of one of Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , TiO 2 , HfO 2 , ZrO 2 , Gd 2 O 3 , La x Al 2-x O 3 , or LaAlO.  
   
   
       5 . The transistor of  claim 1  wherein the gate insulator composition adjacent to the substrate is closer to one of Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , TiO 2 , HfO 2 , ZrO 2 , Gd 2 O 3 , La x Al 2-x O 3 , or LaAlO than the film composition adjacent to the floating gate.  
   
   
       6 . The transistor of  claim 1  wherein the gate insulator composition adjacent to the floating gate is closer to one of Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 5 , TiO 2 , HfO 2 , ZrO 2 , Gd 2 O 3 , La x Al 2-x O 3 , or LaAlO than the film composition adjacent to the substrate.  
   
   
       7 . The transistor of  claim 1  wherein the source/drain regions are n+ conductivity and the substrate is p+ conductivity.  
   
   
       8 . The transistor of  claim 1  wherein the floating gate and control gate are comprised of a polysilicon material.  
   
   
       9 . The transistor of  claim 1  wherein a direction of operation of the transistor determines which source/drain region is a source and which is a drain.  
   
   
       10 . The transistor of  claim 1  wherein the gate insulator is fabricated using electron-gun evaporation.  
   
   
       11 . The transistor of  claim 1  wherein the gate insulator is fabricated using thermal evaporation.  
   
   
       12 . A flash memory transistor comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate, a channel region formed between each pair of source/drain regions;    a graded composition, high dielectric constant gate insulator formed on top of the substrate and substantially adjacent to the channel region, the gate insulator having a dielectric constant that is greater than 3.9 and an electron barrier between the substrate and the gate insulator is in a range of 1.0-2.8 eV;    a floating gate formed on top of the gate insulator;    an oxide insulator formed on top of the floating gate; and    a control gate formed on top of the oxide insulator.    
   
   
       13 . The transistor of  claim 12  wherein the source/drain regions are p+ conductivity and the substrate is n+ conductivity.  
   
   
       14 . A flash memory transistor comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate, a channel region formed between each pair of source/drain regions;    a graded composition, high dielectric constant gate insulator formed on top of the substrate and substantially adjacent to the channel region, the gate insulator having a dielectric constant that is greater than 3.9;    a floating gate formed on top of the gate insulator;    an oxide insulator formed on top of the floating gate; and    a control gate formed on top of the oxide insulator wherein there is an electron barrier between the gate insulator and the floating gate in a range of 1.0-2.8 eV.    
   
   
       15 . A method for fabricating a flash memory cell transistor, the method comprising: creating a plurality of source/drain regions by doping portions of a substrate; 
 depositing a graded composition, high-k gate insulator on the substrate by an evaporation technique substantially between the plurality of source/drain regions, the gate insulator having a dielectric constant that is greater than 3.9;    depositing a floating gate on the gate insulator;    depositing an oxide insulator material on the floating gate; and    forming a control gate on the oxide insulator material.    
   
   
       16 . The method of  claim 15  wherein the evaporation technique comprises evaporation from a high purity TiO 2  slug in a vacuum evaporator with an ion beam.  
   
   
       17 . The method of  claim 15  wherein a portion of the gate insulator adjacent the substrate comprises more of the high-k dielectric material than remaining portions of the gate insulator.  
   
   
       18 . The method of  claim 15  wherein a portion of the gate insulator adjacent the floating gate comprises more of the high-k dielectric material than remaining portions of the gate insulator.  
   
   
       19 . The method of  claim 15  wherein the evaporation technique comprises electron-beam evaporation from a high purity Hf metal slug with a substrate temperature less than 200° C. and subsequent oxidizing.  
   
   
       20 . The method of  claim 15  wherein the evaporation technique on the high-k dielectric material is performed by electron-beam evaporation.  
   
   
       21 . The method of  claim 15  wherein the evaporation technique comprises depositing a Zr film on the substrate by thermal evaporation and subsequently oxidizing the Zr film.  
   
   
       22 . The method of  claim 15  wherein the evaporation technique comprises depositing one of a Y or a Gd film on the substrate by thermal evaporation and subsequently oxidizing the film.  
   
   
       23 . The method of  claim 22  wherein the depositing one of the Y or the Gd film comprises electron-beam evaporation of a high purity Y or Gd metal slug at a substrate temperature less than 200° C.  
   
   
       24 . The method of  claim 15  wherein the evaporation technique comprises depositing a LaAlO 3  film on the substrate and subsequently annealing.  
   
   
       25 . The method of  claim 24  wherein depositing the LaAlO 3  film comprises evaporation of Al 2 O 3  and La 2 O 3  using an electron gun for each material and the annealing is performed at 700° C. in an N 2  ambience.  
   
   
       26 . The method of  claim 24  wherein the annealing is performed at 800-900° C. in RTA for a time in a range of 10-15 seconds in an N 2  ambience.  
   
   
       27 . A flash memory transistor comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;    depositing a graded composition, high-k gate insulator on the substrate by an atomic layer deposition (ALD) technique used on a high-k material, the gate insulator deposited substantially between the plurality of source/drain regions and having a dielectric constant that is greater than 3.9;    a floating gate layer formed on top of the gate insulator;    an oxide insulator formed on top of the floating gate layer; and    a control gate formed on top of the oxide insulator.    
   
   
       28 . The transistor of  claim 27  wherein the high-k material is comprised of one of AlO x , LaAlO 3 , Zr—Ti—O films, or HfO 2 /Hf.  
   
   
       29 . An electronic system comprising: 
 a processor that generates control signals; and    a memory array coupled to the processor, the array comprising a plurality of flash memory cells, each flash memory cell comprising: 
 creating a plurality of source/drain regions by doping portions of a substrate;  
 depositing a graded composition, high-k gate insulator on the substrate by an evaporation technique substantially between the plurality of source/drain regions, the gate insulator having a dielectric constant that is greater than 3.9;  
 depositing a floating gate on the gate insulator;  
 depositing an oxide insulator material on the floating gate; and  
 forming a control gate on the oxide insulator material.  
   
   
   
       30 . The method of  claim 29  wherein the plurality of source/drain regions are created with an n+ conductivity in a p+ substrate.  
   
   
       31 . An electronic system comprising: 
 a processor that generates control signals; and    a memory array coupled to the processor, the array comprising a plurality of flash memory cells, each flash memory cell comprising: 
 a substrate having a plurality of source/drain regions, the source/drain regions having a different conductivity than the remainder of the substrate;  
 depositing a graded composition, high-k gate insulator on the substrate by an atomic layer deposition (ALD) technique used on a high-k material, the gate insulator deposited substantially between the plurality of source/drain regions and having a dielectric constant that is greater than 3.9;  
 a floating gate layer formed on top of the gate insulator;  
 an oxide insulator formed on top of the floating gate layer; and  
 a control gate formed on top of the oxide insulator.