Diagnostic memory dump method in a redundant processor

Abstract

A plurality of redundant, loosely-coupled processor elements are operational as a logical processor. A logic detects a halt condition of the logical processor and, in response to the halt condition, reintegrates and commences operation in less than all of the processor elements leaving at least one processor element nonoperational. The logic also buffers data from the nonoperational processor element in the reloaded operational processor elements and writes the buffered data to storage for analysis.

1 . A method for performing a diagnostic memory dump comprising: 
 detecting a halt condition of at least one processor element of multiple redundant processor elements;    maintaining one processor element in a state existing at the halt condition;    reloading others of the processor elements whereby the others commence execution;    copying the state of the maintained one processor element to a storage while the others continue executing; and    reintegrating the one processor element when the halt condition copying is complete whereby the one processor element commences execution.    
     
     
         2 . The method according to  claim 1  wherein: 
 the multiple redundant processor elements are loosely-synchronized processor elements.    
     
     
         3 . The method according to  claim 1  further comprising: 
 copying memory of the maintained one processor element to buffers in the executing others of the processor elements using a Direct Memory Access (DMA) operation; and    subsequently writing the copied memory to a storage device for later analysis.    
     
     
         4 . The method according to  claim 1  further comprising: 
 initiating a response to a halt condition of a logical processor that comprises a plurality of redundant processor elements;    issuing a command to place the logical processor in a “ready for reload” state, the command designating a processor element that is omitted from reintegration; and    executing the command further comprising: 
 voting-out the designated omitted processor element; and  
 reintegrating remaining processor elements.  
   
     
     
         5 . The method according to  claim 1  further comprising: 
 detecting completion of reintegrating the others of the processor elements; and    automatically initiating a parallel receive dump program; and    executing the parallel receive dump program further comprising: 
 creating a dump file;  
 allocating buffers; and  
 saving architectural state of all processor elements in memory.  
   
     
     
         6 . The method according to  claim 5  wherein executing the parallel receive dump program further comprises: 
 opening a memory window on a memory physical partition; and    moving the window over the partition.    
     
     
         7 . The method according to  claim 5  wherein executing the parallel receive dump program further comprises: 
 executing a divergent data Direct Memory Access (DMA) operation with a self-directed write whereby a designated source memory address identifies the one processor element maintained in the halt condition.    
     
     
         8 . The method according to  claim 6  wherein executing the parallel receive dump program further comprises: 
 upon completion of the Input/Output operation of the divergent DMA operation, compressing data into dump format and writing the compressed data to a dump file; and    closing the memory window.    
     
     
         9 . A computing system comprising: 
 a plurality of redundant, loosely-coupled processor elements operational as a logical processor; and    a logic that detects a halt condition of the logical processor and, in response to the halt condition, reintegrates and commences operation in less than all of the processor elements leaving at least one processor element nonoperational, buffers data from the nonoperational processor element in the reintegrated operational processor elements, and writes the buffered data to storage for analysis.    
     
     
         10 . The computing system according to  claim 9  further comprising: 
 a logic that reloads and reintegrates the nonoperational processor element into the logical processor after the data is buffered.    
     
     
         11 . The computing system according to  claim 9  further comprising: 
 a parallel receive dump program that is initiated after reload and commencement of the operational processor elements, the parallel receive dump program that creates a dump file and allocates the buffers, and saves architectural state of the processor elements in a memory.    
     
     
         12 . The computing system according to  claim 11  further comprising: 
 the parallel receive dump program that opens a memory window on a physical partition allocated to a processor element upon which the parallel receive dump program executes, and that moves the memory window over the entire physical partition.    
     
     
         13 . The computing system according to  claim 12  further comprising: 
 a direct memory access device coupled to the processor element plurality; and    the parallel receive dump program that executes a divergent data input/output operation using the direct memory access device that identifies the nonoperational processor element and transfers data from the nonoperational processor element to at least one operational processor element by direct memory access.    
     
     
         14 . The computing system according to  claim 13  wherein: 
 the parallel receive dump program identifies the nonoperational processor element using address bits.    
     
     
         15 . The computing system according to  claim 13  further comprising: 
 an engine that generates data transfer request packets and tracks associated response packets;    an access validation and translation module that verifies legitimacy of incoming data transfer packets and translates addresses of legitimate packets into internal memory space; and    the parallel receive dump program that holds block transfer engine descriptors and access validation and translation tables in the operational processor elements for managing the direct memory access operation.    
     
     
         16 . The computing system according to  claim 13  further comprising: 
 a reintegration logic that restarts and resynchronizes the plurality of processor elements following a failure or service condition; and    a reintegration process executable on at least one of the operating processor elements that delays reintegrating the nonoperational processor element until dump processing is complete.    
     
     
         17 . The computing system according to  claim 13  wherein: 
 the parallel receive dump program determines when data transfer from the nonoperational processor element to the at least one operational processor element is complete and, upon completion, compresses the transferred data into a dump format and writes the compressed data to a dump file.    
     
     
         18 . The computing system according to  claim 17  wherein: 
 the parallel receive dump program determines when writing of the compressed data to the dump file is complete and, upon completion, closes the window to physical memory, closes the dump file, and initiates reintegration of the nonoperational processor element.    
     
     
         19 . An interface for usage in a redundant processor comprising: 
 a direct memory access device coupled to a plurality of redundant, loosely-coupled processor elements operational as a logical processor; and    a data transfer program that executes a divergent data input/output operation using the direct memory access device that transfers data from one source processor element of the processor element plurality to at least one target processor element of others in the plurality of processor elements by direct memory access.    
     
     
         20 . The interface according to  claim 19  wherein: 
 the data transfer program identifies the source processor element using address bits.    
     
     
         21 . The interface according to  claim 19  further comprising: 
 an engine that generates data transfer request packets and tracks associated response packets;    an access validation and translation module that verifies legitimacy of incoming data transfer packets and translates addresses of legitimate packets into internal memory space; and    the data transfer program that holds block transfer engine descriptors and access validation and translation tables in the operational processor elements for managing the direct memory access operation.    
     
     
         22 . The interface according to  claim 19  further comprising: 
 a reintegration logic restarts and resynchronizes the plurality of processor elements following a failure or service condition; and    a reintegration process executable on at least one of the processor elements that delays reintegrating a selected nonoperational processor element.    
     
     
         23 . A method for performing a diagnostic memory dump comprising: 
 detecting a halt condition of at least one processor element of multiple redundant processor elements;    maintaining one processor element in a state existing at the halt condition;    reloading others of the processor elements whereby the others commence execution;    copying the state and memory of the maintained one processor element, the state being copied to a storage while the others continue executing, the memory being copied to buffers in the executing others of the processor elements using a Direct Memory Access (DMA) operation; and    subsequently writing the copied memory to a storage device for later analysis.    
     
     
         24 . The method according to  claim 23  further comprising: 
 reintegrating the one processor element when the halt condition copying is complete whereby the one processor element commences execution.