Video data processing and processor arrangements

Abstract

Consistent with one aspect, a circuit arrangement performs a variety of operations for tasks relating to motion estimation and includes memories having addressable locations (e.g., N pixels in width) and having various write and read ports, and various ALU components such as multiplexers and adders.

1 . An apparatus for performing a variety of operations relating to motion estimation, including pixel differences, sum of absolute pixel differences, and pixel averaging, comprising: 
 a first memory having a plurality of addressable locations N pixels in width, a first write port, and first and second read ports, wherein X pixels from any one of said addressable locations are accessible in parallel on each of said first and second read ports during an address cycle, X being at least N;    a second memory having a plurality of addressable locations greater than N pixels in width, a second write port, and third and fourth read ports, wherein any X contiguous pixels from any one of said addressable locations are accessible in parallel on each of said third and fourth read ports during an address cycle;    a first multiplexer having one input port coupled to said first and second read ports, another input port coupled to said third read port, and an output port;    a second multiplexer having one input port coupled to said third and fourth read ports, another input port coupled to said fourth read port, and an output port;    an arithmetic unit having a first operand input port coupled to the output port of said first multiplexer, a second operand input port coupled to the output port of said second multiplexer, a first output port for furnishing the absolute value of a difference between a first and second operandi, and a second output port for selectively furnishing one of a difference between said first and second operandi, and an average of said first and second operandi; and    an adder coupled to the first output port of said arithmetic unit; 
 wherein the second output port of said arithmetic unit is routed to said first and second write ports.  
   
   
   
       2 . An apparatus as in  claim 1 , wherein said adder is a tree adder.  
   
   
       3 . A pixel-group random access memory (“PRAM”) having a plurality of addressable locations greater than N pixels in width and a read port, wherein any N contiguous pixels from any one of said addressable locations are accessible in parallel on said read port during an address cycle comprising: 
 a memory array having a plurality of addressable locations N pixels in width and a read port, wherein N pixels from any one of said addressable locations and N pixels from an adjacent addressable location are accessible in parallel on the read port of said memory array during an address cycle, and    a shifter having an input coupled to the read port of said memory array and an output N pixels in width, the output of said shifter being the read port of said PRAM memory.    
   
   
       4 . A circuit as in  claim 3 , wherein said memory array is random access memory.  
   
   
       5 . A circuit as in  claim 3 , wherein said shifter is adapted to perform from zero to N−1 shifts on a pixel boundary.  
   
   
       6 . A method for motion estimation, comprising the steps of: 
 storing an image block matrix having a width of N pixels and a height of M pixels in a first memory;    storing a search window matrix having a width of greater than N pixels and a height of at least M pixels in a second memory;    selecting a search block matrix having a width of N pixels and a height of M pixels from said search window;    determining absolute differences between each of the N×M pixels of the image block matrix and a pixel in a corresponding location of the search block matrix;    summing the absolute differences;    repeating said search block selecting step, said absolute differences determining step, and said summing step for all search blocks from said search window;    identifying the the search block from said search window resulting in the least sum of absolute differences.    
   
   
       7 . A method as in  claim 6 , wherein the step of selecting a search block within said search window comprises the step of skipping every I search blocks, wherein I is any positive integer.  
   
   
       8 . An apparatus for performing digital image motion estimation, comprising: 
 means for storing an image block matrix having a width of N pixels and a height of M pixels in a first memory;    means for storing a search window matrix having a width of greater than N pixels and a height of at least M pixels in a second memory;    means for selecting a search block matrix having a width of N pixels and a height of M pixels from said search window;    means for determining absolute differences between each of the N×M pixels of the image block matrix and a pixel in a corresponding location of the search block matrix;    means for summing the absolute differences;    means for repeating said search block selecting step, said absolute differences determining step, and said summing step for all search blocks from said [repeated] search window; and    means for identifying the search block from said search window resulting in the least sum of absolute differences.