Semiconductor memories

Abstract

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

1 . A semiconductor memory comprising: 
 a plurality of memory cells each including a storage transistor and a semiconductor write device;    a plurality of word lines coupled to the plurality of memory cells and controlling the plurality of memory cells;    a plurality of data lines coupled to the plurality of memory cells and supplied a data signal from the plurality of memory cells;    wherein the storage transistor has a gate terminal electrically coupled to a storage node,    wherein the semiconductor write device has a source region and a drain region and supplies an information voltage to the storage node,    wherein the source and drain of the semiconductor write device is formed by a metal or semiconductor material connected by a channel which is formed by a semiconductor material,    wherein a thickness of the source region and the drain region of the semiconductor write device is larger than a thickness of the channel of the semiconductor write device.    
   
   
       2 . A semiconductor memory according to  claim 1 , 
 wherein the thickness of the channel of semiconductor write device is no more than 5 nanometers.    
   
   
       3 . A semiconductor memory according to  claim 1 , 
 wherein the plurality of data lines include a plurality of the read data lines and a plurality of write data lines,    wherein the plurality of read data lines is supplied the data signal from the plurality of memory cells, and    wherein the plurality of write data lines supply the information voltage to the plurality of memory cells.    
   
   
       4 . A semiconductor memory according to  claim 3 , 
 wherein each of the plurality of memory cells further has a read transistor,    wherein one of a source or a drain of the read transistor is coupled to one of the plurality of read data lines,    wherein the other one of the source or the drain of the read transistor is coupled to the one of a source or a drain of the storage transistor, and    wherein the other one of the source or the drain of the storage transistor is coupled to a predetermined voltage.    
   
   
       5 . A semiconductor memory according to  claim 4 , 
 wherein the plurality of the word lines includes a plurality of read word lines and a plurality of write word lines,    wherein a gate of the semiconductor write device is coupled to one of the plurality of write word lines,    wherein a gate of the read transistor is coupled to one of the plurality of read word lines.    
   
   
       6 . A semiconductor memory comprising: 
 a plurality of read data lines;    a plurality of write data lines;    a plurality of memory cells coupled to the plurality of read data lines and the plurality of write data lines;    wherein each of the plurality of memory cells includes a storage transistor, a read transistor, and a write transistor,    wherein a source and a drain of the write transistor are coupled between one of the plurality of write data lines and a gate of the storage transistor,    wherein a source and a drain of the read transistor are coupled between one of a source or a drain of the storage transistor and one of plurality of read data lines,    wherein the source and the drain of the storage transistor are coupled between one of the source or the drain of the read transistor and a predetermined voltage, and    wherein the write transistor has a channel whose a thickness is larger than a thickness of the drain and the source of the write transistor.    
   
   
       7 . A semiconductor memory according to  claim 6 , further comprising: 
 a plurality of read word lines;    a plurality of write word lines;    wherein a gate of the read transistor is coupled to one of the plurality of read word lines and    wherein a gate of the write transistor is coupled to one of the plurality of write word lines.    
   
   
       8 . A semiconductor memory according to  claim 6 , 
 wherein the thickness of the channel of semiconductor write device is no more than 5 nanometers.    
   
   
       9 . A semiconductor memory according to  claim 6 , 
 wherein the storage transistor is an N-channel MOS device.