Non-volatile semiconductor memory and manufacturing method thereof

Abstract

An enhanced non-volatile semiconductor memory has a source region and a drain region provided in a semiconductor substrate, an electric charge accumulating portion provided on a channel region between the source and drain regions and a control gate provided on said channel region and at least said source region is provided by introducing an impurity in self-alignment with a side wall provided on a side surface of said control gate, characterized in that an overlap of said drain region with said electric charge accumulating portion is set larger than an overlap of said source region with said electric charge accumulating portion, and an impurity dose quantity of said source region is larger than an impurity dose quantity of said drain region. The drain region may be formed by self alignment manner using a first side wall and the source region may be formed by self alignment manner using a second side wall formed on the first side wall.

1 - 6 . (canceled)  
   
   
       7 . A method of manufacturing a non-volatile semiconductor memory, comprising: 
 a step of providing a control gate trough through an electric charge accumulating portion on a semiconductor substrate;    a step of providing a drain region by introducing an impurity outwardly of one edge of said control gate on said semiconductor substrate in self-alignment with the edge thereof;    a step of providing a side wall insulating layer on a side surface of said control gate; and    a step of providing a source region by introducing the impurity outwardly of said side wall insulating layer on said semiconductor substrate in self-alignment with said side wall insulating layer.    
   
   
       8 . The method according to  claim 7 , wherein an impurity dose quantity of said source region is set, larger than an impurity dose quantity of said drain region.  
   
   
       9 . The method according to  claim 7 , wherein the impurity is introduced deeper in said source region than in said drain region.  
   
   
       10 . A method of manufacturing a non-volatile semiconductor memory, comprising: 
 a step of providing a floating gate material layer through a channel insulating layer on a semiconductor substrate;    a step of providing a control gate material layer through an inter-layer insulating layer on said floating gate material layer;    a step of providing a control gate and a floating gate by sequentially patterning said control gate material layer and said floating gate material layer;    a step of providing a drain region by introducing an impurity outwardly of one edge of said control gate on said semiconductor substrate in self-alignment with the edge thereof;    a step of providing a side wall insulating layer on side surfaces of said control gate and of said floating gate; and    a step of providing a source region by introducing the impurity outwardly of said side wall insulating layer on said semiconductor substrate in self-alignment with said side wall insulating layer.    
   
   
       11 . The method according to  claim 10 , wherein an impurity dose quantity of said source region is set larger than an impurity dose quantity of said drain region.  
   
   
       12 . The method according to  claim 10 , wherein the impurity is introduced deeper in said source region than in said drain region.  
   
   
       13 . A method of manufacturing a non-volatile semiconductor memory, comprising: 
 a step of providing a control gate trough an electric charge, accumulating portion on a semiconductor substrate;    a step of providing a first side wall insulating layer on a side surface of said control gate;    a step of providing a drain region by introducing an impurity outwardly of said first side wall insulating layer on said semiconductor substrate in self-alignment with said first side wall insulating layer;    a step of providing a second side wall insulating layer on a side surface of said first side wall insulating layer; and    a step of providing a source region by introducing the impurity outwardly of said second side wall insulating layer on said semiconductor substrate in self-alignment with said second side wall insulating layer.    
   
   
       14 . The method according to  claim 13 , wherein an impurity dose quantity of said source region is set larger than an impurity dose quantity of said drain region.  
   
   
       15 . The method according to  claim 14 , wherein the impurity is introduced deeper in said source region than in said drain region.  
   
   
       16 . A method of manufacturing a non-volatile semiconductor memory, comprising: 
 a step of providing a floating gate material layer through a channel insulating layer on a semiconductor substrate;    a step of providing a control gate material layer through an inter-layer insulating layer on said floating gate material layer;    a step of providing a control gate and a floating gate by sequentially patterning said control gate material layer and said floating gate material layer;    a step of providing a first side wall insulating layer on side surfaces of said control gate and of said floating gate;    a step of providing a drain region by introducing an impurity outwardly of said first side wall insulating layer on said semiconductor substrate in self-alignment with said first side wall insulating layer;    a step of providing a second side wall insulating layer on a side surface of said first side wall insulating layer; and    a step of providing a source region by introducing the impurity outwardly of said second side wall insulating layer on said semiconductor substrate in self-alignment with said second side wall insulating layer.    
   
   
       17 . A method of manufacturing a non-volatile semiconductor memory according to  claim 16 , wherein an impurity dose quantity of said source region is set larger than an impurity dose quantity of said drain region.  
   
   
       18 . A method of manufacturing a non-volatile semiconductor memory according to  claim 16 , wherein the impurity is introduced deeper in said source region than in said drain region.