US2005230746A1PendingUtilityA1

Power semiconductor switching devices and power semiconductor devices

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Individually held — no corporate assignee on recordPriority: Jul 13, 2000Filed: Mar 24, 2005Published: Oct 20, 2005
Est. expiryJul 13, 2020(expired)· nominal 20-yr term from priority
Inventors:Richard C. EdenBruce A. Smetana
H02M 3/33592H02M 3/33507H02M 3/33576H10W 90/724H10W 72/251H10W 70/681H10W 72/00H10W 70/685H10W 70/635H10W 70/65H10W 44/601H10W 20/484H10W 72/20H10D 30/66H10D 84/83H10D 64/519H10D 64/251H10D 30/60Y02B70/10
40
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Claims

Abstract

Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Claims

exact text as granted — not AI-modified
1 . A power semiconductor switching device comprising: 
 a semiconductive substrate having a surface;    a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent to the surface; and    an energy storage device coupled with the power transistor and configured to assist switching of the power transistor.    
   
   
       2 . The device of  claim 1  wherein the power transistor comprises at least one thousand electrically coupled sources and at least one thousand electrically coupled drains.  
   
   
       3 . The device of  claim 1  wherein the power transistor comprises a plurality of electrically coupled gates.  
   
   
       4 . The device of  claim 1  wherein the power transistor is configured to conduct power currents in excess of one Ampere.  
   
   
       5 . The device of  claim 1  wherein the semiconductive substrate comprises a flip chip semiconductive die.  
   
   
       6 . The device of  claim 1  further comprising a body diode circuit coupled intermediate the sources and the drains.  
   
   
       7 . The device of  claim 6  wherein the body diode circuit comprises a n-channel field effect transistor having a gate and a source electrically coupled.  
   
   
       8 . The device of  claim 6  wherein the body diode circuit comprises a p-channel field effect transistor.  
   
   
       9 . The device of  claim 1  wherein the power transistor comprises a plurality of parallel-coupled field effect transistors.  
   
   
       10 . The device of  claim 1  further comprising a V dd  contact, and wherein the energy storage device comprises a bypass capacitor electrically coupled with the V dd  contact and the sources.  
   
   
       11 . The device of  claim 10  wherein the power transistor comprises a plurality of gates, and the bypass capacitor is configured to charge a capacitance of the gates to assist the switching of the power transistor.  
   
   
       12 . The device of  claim 1  wherein the power transistor comprises a plurality of planar MOSFET devices.  
   
   
       13 . A power semiconductor device comprising: 
 a semiconductive substrate;    a semiconductor device comprising at least one thousand planar field effect transistors formed using the substrate and wherein individual ones of the field effect transistors include a source and a drain electrically coupled with other sources and drains of the other planar field effect transistors; and    a circuit configured to selectively conduct currents intermediate a source and a drain of the semiconductor device.    
   
   
       14 . The device of  claim 13  wherein the at least one thousand planar field effect transistors individually include a gate, and the gates of the at least one thousand planar field effect transistors are electrically coupled to receive a common control signal.  
   
   
       15 . The device of  claim 13  wherein the semiconductor device is configured to conduct power currents in excess of one Ampere.  
   
   
       16 . The device of  claim 13  wherein the semiconductive substrate comprises a flip chip semiconductive die.  
   
   
       17 . The device of  claim 13  wherein the circuit comprises a body diode circuit coupled intermediate the sources and the drains of the planar field effect transistors.  
   
   
       18 . The device of  claim 17  wherein the body diode circuit comprises a n-channel field effect transistor having a gate and a source electrically coupled.  
   
   
       19 . The device of  claim 17  wherein the body diode circuit comprises a p-channel field effect transistor.  
   
   
       20 . The device of  claim 13  further comprising: 
 a V dd  contact; and    a bypass capacitor electrically coupled with the V dd  contact and the sources.    
   
   
       21 . The device of  claim 20  wherein the power transistor comprises a plurality of gates, and the bypass capacitor is configured to charge a capacitance of the gates.  
   
   
       22 . The device of  claim 13  wherein the at least one thousand planar field effect transistors comprise MOSFET devices.  
   
   
       23 . A power semiconductor switching device comprising a plurality of planar submicron field effect transistor devices coupled in parallel and configured to selectively conduct power currents in excess of one Ampere; and 
 an energy storage device configured to assist switching of the field effect transistor devices.    
   
   
       24 . A power semiconductor switching device comprising a plurality of field effect transistors having source contacts and drain contacts formed adjacent to a common surface of a semiconductive substrate and configured to selectively conduct power currents in excess of one Ampere, wherein gates of the field effect transistors are constrained to have a voltage substantially equal to or more positive than a voltage of the source contacts and with respect to a common voltage reference.  
   
   
       25 . A power semiconductor switching device comprising: 
 a monolithic semiconductive substrate having a surface;    a power transistor comprising a source and a drain formed using a monolithic semiconductive substrate and the source and the drain are formed adjacent to the surface; and    an energy storage device formed using the monolithic semiconductive substrate and configured to assist switching of the power transistor.    
   
   
       26 . A power semiconductor switching device comprising a flip chip configuration configured to conduct power currents in excess of one Ampere; and wherein semiconductive circuitry of the flip chip configuration configured to implement the conduction of the power currents is further configured to form body diode circuitry.  
   
   
       27 - 50 . (canceled)  
   
   
       51 . The device of  claim 1  wherein the energy storage device comprises a bypass capacitor.  
   
   
       52 . The device of  claim 1  wherein the energy storage device is configured to charge a gate capacitance of the power transistor to assist the switching of the power transistor.  
   
   
       53 . The device of  claim 1  wherein the energy storage device is formed using the semiconductive substrate comprising a monolithic substrate.  
   
   
       54 . The device of  claim 13  wherein the circuit is configured to conduct free wheeling currents.  
   
   
       55 . The device of  claim 13  wherein the circuit is configured to conduct currents when a voltage at a drain of the power transistor is more negative than a source of the power transistor with respect to a common voltage reference.  
   
   
       56 . The device of  claim 13  wherein the circuit comprises an active diode connected field effect transistor.  
   
   
       57 . The device of  claim 56  wherein the active diode field effect transistor comprises a p-channel device having a gate of the p-channel device electrically coupled with a drain of the p-channel device.  
   
   
       58 . The device of  claim 13  wherein the circuit is configured to enable the semiconductor device to switch at an increased switching speed compared with a switching speed of the semiconductor device in the absence of the circuit.  
   
   
       59 . The device of  claim 23  wherein the energy storage device comprises a bypass capacitor.  
   
   
       60 . The device of  claim 23  wherein the energy storage device is configured to charge a gate capacitance of the field effect transistor devices to assist the switching of the field effect transistor devices.  
   
   
       61 . The device of  claim 25  wherein the energy storage device comprises a bypass capacitor.  
   
   
       62 . The device of  claim 25  wherein the energy storage device is configured to charge a gate capacitance of the power transistor to assist the switching of the power transistor.

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