Internal evict with external request

Abstract

A cache is configured to select a cache block for eviction in response to detecting a cache miss. The cache transmits the address of the cache block as a write transaction on an interface to the cache, and the cache captures the address from the interface and reads the cache block from the cache memory in response to the address. The read may occur similar to other reads in the cache, detecting a hit in the cache (in the cache storage location from which the cache block is being evicted). The write transaction is initiated before the corresponding data is available for transfer, and the use of the bus bandwidth to initiate the transaction provides an open access time into the cache for reading the evicted cache block.

1 - 8 . (canceled)  
   
   
       9 . A cache comprising: 
 a memory configured to store a plurality of cache blocks; and    a control circuit configured to transmit an address of a cache block to be evicted from the cache on an interface to which the cache is couplable;    wherein the memory is coupled to receive the address from the interface and is configured to access the cache block in response to the address for transmission on the interface.    
   
   
       10 . The cache as recited in  claim 9  wherein the control circuit is configured to detect a miss in the cache and to select the cache block from the plurality of cache blocks in response to detecting the miss.  
   
   
       11 . The cache as recited in  claim 10  further comprising a tag memory coupled to receive a second address from the interface and configured to output a plurality of tags corresponding to cache storage locations eligible to store a second cache block addressed by the second address, wherein the control circuit is configured to select a first cache storage location of the cache storage locations to store the second cache block if the second address is a miss in the cache, and wherein the address of the cache block comprises a first tag of the plurality of tags, the first tag corresponding to the first cache storage location.  
   
   
       12 . The cache as recited in  claim 11  further comprising a plurality of comparators, each of the plurality of comparators coupled to receive a respective one of the plurality of tags and a tag portion of the second address, and wherein the plurality of comparators are configured to compare the plurality of tags to the tag portion of the second address and are coupled to provide an indication of the comparison to the control circuit.  
   
   
       13 - 20 . (canceled)