Solid-state circuit assembly

Abstract

The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

1 . A semiconductor substrate comprising: 
 a first doping region comprising a first conduction type;    a second doping region comprising a second conduction type formed at least in part in the first doping region, the second conduction type being opposite to the first conduction type;    a highly doped connection region comprising the second conduction type, the highly doped connection region formed at least in part in the second doping region;    an insulation layer formed on a surface of the first doping region, second doping region, and highly doped connection region;    an electrically conductive structure, extending through the insulation layer and electrically connected to the highly doped connection region; and    a highly doped discharge region comprising the second conduction type, the highly doped discharge region formed in at least the first and second doping regions.    
   
   
       2 . The semiconductor substrate of  claim 1 , wherein the highly doped discharge region is a diffusion strip formed in a junction between the first and second doping regions.  
   
   
       3 . The semiconductor substrate of  claim 1 , wherein a ratio of the surface area of the second doping region to the surface area of the electrically conductive structure is greater than  10 .  
   
   
       4 . The semiconductor substrate of  claim 1 , wherein the electrically conductive structure comprises at least one Cu interconnect layer produced using a Damascene process.  
   
   
       5 . The semiconductor substrate of  claim 1 , wherein the highly doped discharge region is formed at a surface of the semiconductor substrate.  
   
   
       6 . A semiconductor substrate comprising: 
 a first doping region comprising a first conduction type;    a second doping region comprising a second conduction type formed at least in part in the first doping region, the second conduction type being opposite to the first conduction type;    a highly doped connection/discharge region comprising the second conduction type, the highly doped connection/discharge region formed in at least the first and second doping regions;    an insulation layer formed on a surface of the first doping region, second doping region, and high doped connection/discharge region; and    an electrically conductive structure, extending through the insulation layer and electrically connected with the highly doped connection/discharge region.    
   
   
       7 . The semiconductor substrate of  claim 6 , wherein the electrically conductive structure comprises at least one Cu interconnect layer produced using a Damascene process.  
   
   
       8 . The semiconductor substrate of  claim 6 , wherein a ratio of the surface area of the second doping region to the surface area of the electrically conductive structure is greater than  10 .  
   
   
       9 . The semiconductor substrate of  claim 6 , wherein the highly doped connection/discharge region is formed at a surface of the semiconductor substrate.  
   
   
       10 . A semiconductor substrate comprising: 
 a first doping region comprising a first conduction type;    a second doping region comprising a second conduction type formed at least in part in the first doping region, the second conduction type being opposite to the first conduction type;    a third doping region comprising the first conduction type, the third doping region formed at least in part in the second doping region;    a highly doped connection region comprising the first conduction type formed at least in part in the third doping region;    a first highly doped discharge region comprising the first conduction type formed in at least the second and third doping regions;    a second highly doped discharge region comprising the second conduction type formed in at least the first and second doping regions;    an insulation layer formed on a surface of the fist doping region, second doping region, third doping region, highly doped connection region, first highly doped discharge region, and second highly doped discharge region; and    an electrically conductive structure, extending through the insulation layer and electrically connected to the highly doped connection region.    
   
   
       11 . The semiconductor substrate of  claim 10 , where the first highly doped discharge region is a diffusion strip formed in a junction between the second and third doping regions.  
   
   
       12 . The semiconductor substrate of  claim 10 , where the second highly doped discharge region is a diffusion strip formed in a junction between the first and second doping regions.  
   
   
       13 . The semiconductor substrate of  claim 10 , wherein the electrically conductive structure comprises at least one Cu interconnect layer produced using a Damascene process.  
   
   
       14 . The semiconductor substrate of  claim 10 , wherein a ratio of the surface area of the third doping region to the surface area of the electrically conductive structure is greater than 10.  
   
   
       15 . The semiconductor substrate of  claim 10 , wherein the first and second highly doped discharge regions are formed at a surface of the semiconductor substrate.  
   
   
       16 . A semiconductor substrate comprising: 
 a first doping region comprising a first conduction type;    a second doping region comprising a second conduction type formed at least in part in the first doping region, the second conduction type being opposite to the first conduction type;    a highly doped connection region comprising the second conduction type formed at least in part in the second doping region;    a first highly doped discharge region comprising the second conduction type formed at least in part in the second doping region;    a second highly doped discharge region comprising the second conduction type formed at least in part in the first doping region;    a first insulation layer formed on a surface of the first doping region, second doping region, highly doped connection region, first highly doped discharge region, and second highly doped discharge region;    a second insulation layer formed on a surface of the first insulation layer;    a first electrically conductive structure, extending through the first and second insulation layer and electrically connected to the connection doping region;    an electrically conductive interconnect layer formed in the first insulation layer;    a second electrically conductive structure, extending through the first insulation layer and electrically connected to the first discharge region; and    a third electrically conductive structure, extending through the first insulation layer and electrically connected to the second discharge region.    
   
   
       17 . The semiconductor substrate of  claim 15 , wherein the electrically conductive structure comprises at least one Cu interconnect layer produced using a Damascene process.  
   
   
       18 . The semiconductor substrate of  claim 15 , wherein a ratio of the surface area of the second doping region to the surface area of the electrically conductive structure is greater than  10 .  
   
   
       19 . The semiconductor substrate of  claim 15 , wherein the first and second highly doped discharge regions are formed at a surface of the semiconductor substrate.